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BJ77.
An Unexpected PMI May Occur After Writing a Large Value to
IA32_FIXED_CTR2
Problem:
If the fixed-function performance counter IA32_FIXED_CTR2 MSR (30BH) is configured
to generate a performance-monitor interrupt (PMI) on overflow and the counter's value
is greater than FFFFFFFFFFC0H, then this erratum may incorrectly cause a PMI if
software performs a write to this counter.
Implication:
A PMI may be generated unexpectedly when programming IA32_FIXED_CTR2. Other
than the PMI, the counter programming is not affected by this erratum as the
attempted write operation does succeed.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ78.
RDMSR From The APIC-Timer CCR May Disarm The APIC Timer in TSC
Deadline Mode
Problem:
When in TSC Deadline mode with TSC_Deadline timer armed
(IA32_TSC_DEADLINE<>0, MSR 6E0H), a read from the local APIC's CCR (current
count register) in APIC MMIO space may disarm the TSC Deadline timer without
generating an interrupt as specified in the APIC Timer LVT (Local Vector Table) entry.
Implication:
Due to this erratum, unexpected disarming of the APIC timer and possible loss of an
interrupt may occur.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes
BJ79.
RC6 Entry Can be Blocked by Asynchronous Intel
Problem:
The graphics Command Streamer can get into a state that will effectively inhibit graphic
RC6 (Render C6) power management state entry until render reset occurs. Any
asynchronous Intel VT-d (Virtualization Technology for Directed I/O) access to IOTLB
can potentially cause graphics Command Streamer to get into this RC6 inhibited state.
Implication:
Average power will increase until RC6 is activated with a render reset.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ80.
Repeated PCIe* and/or DMI L1 Transitions During Package Power
States May Cause a System Hang
Problem:
Under a complex set of internal conditions when the processor is in a deep power state
(package C3, C6 or C7) and the PCIe and/or DMI links are toggling in and out of L1
state, internal states of the processor may become inaccessible resulting in a system
hang.
Implication:
Due to this erratum, the system may hang.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
44
®
VT-d Flows
Specification Update
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