Table of Contents
Advertisement
BJ25.
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem:
Under certain conditions as described in the Software Developers Manual section "Out-
of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or may observe memory ordering violations.
Implication:
Upon crossing the page boundary the following may occur, dependent on the new page
memory type:
•
UC the data size of each write will now always be 8 bytes, as opposed to the original
data size.
•
WP the data size of each write will now always be 8 bytes, as opposed to the original
data size and there may be a memory ordering violation.
•
WT there may be a memory ordering violation.
Workaround:
Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ26.
Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Problem:
Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor
uses to access the VMCS and data structures referenced by pointers in the VMCS. Due
to this erratum, a VMX access to the VMCS or referenced data structures will instead
use the memory type that the MTRRs (memory-type range registers) specify for the
physical address of the access.
Implication:
Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory type
will be used but the processor may use a different memory type.
Workaround:
Software should ensure that the VMCS and referenced data structures are located at
physical addresses that are mapped to WB memory type by the MTRRs.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ27.
Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
Problem:
In certain circumstances, when a floating point exception (#MF) is pending during
single-step execution, processing of the single-step debug exception (#DB) may be
mishandled.
Implication:
When this erratum occurs, #DB will be incorrectly handled as follows:
•#DB is signaled before the pending higher priority #MF (Interrupt 16).
•#DB is generated twice on the same instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
28
Specification Update
Hide quick links:
Advertisement
Table of Contents
