Intel BX80623G530 Specification page 11

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Errata (Sheet 2 of 5)
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Specification Update
Status
Reported Memory Type May Not Be Used to Access the VMCS and Referenced
No Fix
Data Structures
No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI
No Fix The Processor May Report a #TS Instead of a #GP Fault
No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction
No Fix Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected
No Fix Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM
No Fix Unsupported PCIe* Upstream Access May Complete with an Incorrect Byte Count
Malformed PCIe* Transactions May be Treated as Unsupported Requests Instead
No Fix
of as Critical Errors
No Fix PCIe* Root Port May Not Initiate Link Speed Change
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/
No Fix
XRSTOR Image Leads to Partial Memory Update
No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
No Fix
Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
No Fix
Wraps a 64-Kbyte Boundary in 16-Bit Code
No Fix Spurious Interrupts May be Generated From the Intel® VT-d Remap Engine
Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation
No Fix
Descriptors
VPHMINPOSUW Instruction in Vex Format Does Not Signal #UD When vex.vvvv
No Fix
!=1111b
LBR, BTM or BTS Records May have Incorrect Branch From Information After an
No Fix
EIST/T-state/S-state/C1E Transition or Adaptive Thermal Throttling
VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported
No Fix
Field in VMCS
No Fix Clock Modulation Duty Cycle Cannot be Programmed to 6.25%
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for
No Fix
VEX.vvvv May Produce a #NM Exception
No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
PCI Express* Graphics Receiver Error Reported When Receiver With L0s Enabled
No Fix
and Link Retrain Performed
No Fix Unexpected #UD on VZEROALL/VZEROUPPER
No Fix Perfmon Event LD_BLOCKS.STORE_FORWARD May Overcount
Conflict Between Processor Graphics Internal Message Cycles And Graphics
No Fix
Reads From Certain Physical Memory Ranges May Cause a System Hang
Execution of Opcode 9BH with the VEX Opcode Extension May Produce a #NM
No Fix
Exception
Executing The GETSEC Instruction While Throttling May Result in a Processor
No Fix
Hang
ERRATA
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