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BJ41.
Fault Not Reported When Setting Reserved Bits of Intel
Invalidation Descriptors
Problem:
Reserved bits in the Queued Invalidation descriptors of Intel VT-d (Virtualization
Technology for Directed I/O) are expected to be zero, meaning that software must
program them as zero while the processor checks if they are not zero. Upon detection
of a non-zero bit in a reserved field, an Intel VT-d fault should be recorded. Due to this
erratum, the processor does not check reserved bit values for Queued Invalidation
descriptors.
Implication:
Due to this erratum, faults will not be reported when writing to reserved bits of Intel
VT-d Queued Invalidation Descriptors.
Workaround:
None identified
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ42.
VPHMINPOSUW Instruction in Vex Format Does Not Signal #UD When
vex.vvvv !=1111b
Problem:
Processor does not signal #UD fault when executing the reserved instruction
VPHMINPOSUW with vex.vvvv !=1111b.
Implication:
Executing VPHMINPOSUW with vex.vvvv !=1111b results in the same behavior as
executing with vex.vvvv=1111b.
Workaround:
Software should not use VPHMINPOSUW with vex.vvvv !=1111b, in order to ensure
future compatibility.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ43.
LBR, BTM or BTS Records May have Incorrect Branch From
Information After an EIST/T-state/S-state/C1E Transition or Adaptive
Thermal Throttling
Problem:
The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after a
transition of:
•
EIST (Enhanced Intel
•
T-state (Thermal Monitor states).
•
S1-state (ACPI package sleep state).
•
C1E (Enhanced C1 Low Power state).
•
Adaptive Thermal Throttling.
Implication:
When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
"From" addresses for the first branch after a transition of EIST, T-states, S-states, C1E,
or Adaptive Thermal Throttling.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
®
SpeedStep Technology).
®
VT-d Queued
33
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