Intel BX80623G530 Specification page 38

BJ56. Reception of Certain Malformed Transactions May Cause PCIe* Port to
Hang Rather Than Reporting an Error
Problem: If the processor receives an upstream malformed non posted packet for which the type
field is IO, Configuration or the deprecated TCfgRd and the format is 4 DW header, then
due to this erratum the integrated PCIe controller may hang instead of reporting the
malformed packet error or issuing an unsupported request completion transaction.
Implication: Due to this erratum, the processor may hang without reporting errors when receiving a
malformed PCIe transaction. Intel has not observed this erratum with any commercially
available device.
Workaround: None identified. Upstream transaction initiators should avoid issuing unsupported
requests with 4 DW header formats.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ57. PCIe* LTR Incorrectly Reported as Being Supported
Problem: LTR (Latency Tolerance Reporting) is a new optional feature specified in PCIe rev. 2.1.
The processor reports LTR as supported in LTRS bit in DCAP2 register (bus 0; Device 1;
Function 0; offset 0xc4), but this feature is not supported.
Implication: Due to this erratum, LTR is always reported as supported by the LTRS bit in the DCAP2
register.
Workaround: None the identified.
Status: For steppings affected, see the Summary Tables of Changes.
BJ58. Performance-Counter Overflow Indication May Cause Undesired
Behavior
Problem: Under certain conditions (listed below) when a performance counter overflows, its
overflow indication may remain set indefinitely. This erratum affects the general-
purpose performance counters IA32_PMC{0-7} and the fixed-function performance
counters IA32_FIXED_CTR{0-2}. The erratum may occur if any of the following
conditions are applied concurrent to when an actual counter overflow condition is
reached:
1. Software disables the counter either globally through
the IA32_PERF_GLOBAL_CTRL MSR (38FH), or locally through the
IA32_PERFEVTSEL{0-7} MSRs (186H-18DH), or the IA32_FIXED_CTR_CTRL MSR
(38DH).
2. Software sets the IA32_DEBUGCTL MSR (1D9H) FREEZE_PERFMON_ON_PMI bit
[12].
3. The processor attempts to disable the counters by updating the state of the
IA32_PERF_GLOBAL_CTRL MSR (38FH) as part of transitions such as VM exit, VM
entry, SMI, RSM, or processor C-state.
Implication: Due to this erratum, the corresponding overflow status bit in
IA32_PERF_GLOBAL_STATUS MSR (38DH) for an affected counter may not get cleared
when expected. If a corresponding counter is configured to issue a PMI (performance
monitor interrupt), multiple PMIs may be signaled from the same overflow
condition. Likewise, if a corresponding counter is configured in PEBS mode (applies to
only the general purpose counters), multiple PEBS events may be signaled.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
38 Specification Update