Intel BX80623G530 Specification page 14

Errata (Sheet 5 of 5)
Steppings
Number
D-2 Q-0
BJ111 X X
BJ112 X X
BJ113 X X
X X
BJ114
BJ115 X X
BJ116 X X
X X
BJ117
BJ118 X X
BJ119 X X
BJ120 X X
BJ121 X X
BJ122 X X
BJ123 X X
BJ124 X X
BJ125 X X
BJ126 X X
BJ127 X X
BJ128 X X
Specification Changes
Number
None for this revision of this specification update.
Specification Clarifications
Number
None for this revision of this specification update.
14
Status
VM Exits Due to "NMI-Window Exiting" May Not Occur Following a VM Entry to the
No Fix
Shutdown State
Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64-
No Fix
Bit Linear Addresses
No Fix VEX.L is Not Ignored with VCVT*2SI Instructions
No Fix MCI_ADDR May be Incorrect For Cache Parity Errors
Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable
No Fix
Memory
No Fix Reported Maximum Memory Frequency Capability May Be Higher Than Expected
The Processor May Not Properly Execute Code Modified Using A Floating-Point
No Fix
Store
No Fix Execution of GETSEC[SEXIT] May Cause a Debug Exception to be Lost
VM Exits Due to GETSEC May Save an Incorrect Value for "Blocking by STI" in the
No Fix
Context of Probe-Mode Redirection
Specific Graphics Blitter Instructions May Result in Unpredictable Graphics
No Fix
Controller Behavior
No Fix IA32_MC5_CTL2 is Not Cleared by a Warm Reset
Plan Fix Performance Monitor Counters May Produce Incorrect Results
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated
No Fix
After a UC Error is Logged
®
No Fix Spurious Intel VT-d Interrupts May Occur When the PFO Bit is Set
No Fix Processor May Livelock During On Demand Clock Modulation
No Fix The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging
No Fix EPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly
IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The Highest
No Fix
Index Value Used For VMCS Encoding
SPECIFICATION CHANGES
SPECIFICATION CLARIFICATIONS
ERRATA
Specification Update