Intel BX80623G530 Specification page 12

Errata (Sheet 3 of 5)
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12
Status
A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain
No Fix
Conditions
Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was
No Fix
Changed Without Invalidation
Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang
No Fix
Rather Than Reporting an Error
No Fix PCIe* LTR Incorrectly Reported as Being Supported
No Fix Performance-Counter Overflow Indication May Cause Undesired Behavior
XSAVE Executed During Paging-Structure Modification May Cause Unexpected
No Fix
Processor Behavior
No Fix C-state Exit Latencies May be Higher Than Expected
MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control
No Fix
Offset Field
Intel® VT-d Interrupt Remapping Will Not Report a Fault if Interrupt Index Exceeds
No Fix
FFFFH
No Fix PCIe* Link Speed May Not Change From 5.0 GT/s to 2.5 GT/s
No Fix L1 Data Cache Errors May be Logged With Level Set to 1 Instead of 0
An Unexpected Page Fault or EPT Violation May Occur After Another Logical
No Fix
Processor Creates a Valid Translation for a Page
No Fix TSC Deadline Not Armed While in APIC Legacy Mode
No Fix PCIe* Upstream TCfgWr May Cause Unpredictable System Behavior
No Fix Processor May Fail to Acknowledge a TLP Request
Executing The GETSEC Instruction While Throttling May Result in a Processor
No Fix
Hang
No Fix PerfMon Event LOAD_HIT_PRE.SW_PREFETCH May Overcount
Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM
No Fix
Exception
No Fix Unexpected #UD on VPEXTRD/VPINSRD
No Fix Erratum Removed
No Fix Successive Fixed Counter Overflows May be Discarded
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch
No Fix
Instructions
No Fix A Read from The APIC-Timer CCR May Disarm The TSC_Deadline Counter
No Fix An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2
RDMSR From The APIC-Timer CCR May Disarm The APIC Timer in TSC Deadline
No Fix
Mode
No Fix RC6 Entry Can be Blocked by Asynchronous Intel® VT-d Flows
Repeated PCIe* and/or DMI L1 Transitions During Package Power States May
No Fix
Cause a System Hang
No Fix Execution of BIST During Cold RESET Will Result in a Machine Check Shutdown
PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the
No Fix
Specification
ERRATA
Specification Update