Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 52
Specification update
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instead contains 0x160. All fields of the Extended Capability structure at offset 0x160
are 0x0. A Capability ID of 0x0 is a reserved Capability ID.
Implication:
Software that enables features based upon the existence of the AER may not observe
the expected behavior associated with this capability.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO112.
PMIs During Core C6 Transitions May Cause the System to Hang
Problem:
If a performance monitoring counter overflows and causes a PMI (Performance
Monitoring Interrupt) at the same time that the core enters C6, then this may cause
the system to hang.
Implication:
Due to this erratum, the processor may hang when a PMI coincides with core C6 entry.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO113.
IA32_MC8_CTL2 MSR is Not Cleared on Processor Warm Reset
Problem:
After processor warm reset the IA32_MC8_CTL2 MSR (288H) should be zero. Due to
this erratum the IA32_MC8_CTL2 MSR is not zeroed on processor warm reset.
Implication:
When this erratum occurs, the IA32_MC8_CTL2 MSR will not be zeroed by warm reset.
Software that expects the values to be 0 coming out of warm reset may not behave as
expected.
Workaround:
BIOS should zero the IA32_MC8_CTL2 MSR after a warm reset.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO114.
The TPM's Locality 1 Address Space Can Not be Opened
Problem:
Due to this erratum, writing to TXT.CMD.OPEN.LOCALITY1 (FED2_0380H) does not
open the Locality 1 address space to the TPM (Trusted Platform Module).
Implication:
Software that uses the TPM's Locality 1 address space will not be able to gain access to
it.
Workaround:
All operations for the TPM should be done using Locality 0 or Locality 2 instead of
Locality 1.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO115.
The Combination of a Page-Split Lock Access And Data Accesses That
Are Split Across Cacheline Boundaries May Lead to Processor Livelock
Problem:
Under certain complex micro-architectural conditions, the simultaneous occurrence of a
page-split lock and several data accesses that are split across cacheline boundaries
may lead to processor livelock.
Implication:
Due to this erratum, a livelock may occur that can only be terminated by a processor
reset. Intel has not observed this erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO116.
PCIe Link Bit Errors Present During L0s Entry May Cause the System
to Hang During L0s Exit
Problem:
During L0s entry PCIe link bit errors may be generated due to a slow shutdown
response from the PCIe analog circuits. As a result, the PCIe analog circuits may now
52
Specification Update
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