Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 32

AAO40. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode
Interrupt is Received while All Cores in C6
Problem: If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is
pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will
be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1).
However, the pending interrupt event will not be cleared.
Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the
external interrupt. Intel has not observed this erratum with any commercially available
software/system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAO41. Two xAPIC Timer Event Interrupts May Unexpectedly Occur
Problem: If an xAPIC timer event is enabled and while counting down the current count reaches
1 at the same time that the processor thread begins a transition to a low power C-
state, the xAPIC may generate two interrupts instead of the expected one when the
processor returns to C0.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer
event.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAO42. EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
Problem: If core C6 is entered after the start of an interrupt service routine but before a write to
the APIC EOI register, the core may not send an EOI transaction (if needed) and further
interrupts from the same priority level or lower may be blocked.
Implication: EOI transactions and interrupts may be blocked when core C6 is used during interrupt
service routines. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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Specification Update