Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 27
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AAO23.
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem:
A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the sequential
execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an
invalid stack during interrupt handling. However, an enabled debug breakpoint or single
step trap may be taken after MOV SS/POP SS if this instruction is followed by an
instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP
instruction. This results in a debug exception being signaled on an unexpected
instruction boundary since the MOV SS/POP SS and the following instruction should be
executed atomically.
Implication:
This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP,
[r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not observed this erratum with any commercially available
software or system.
Workaround:
As recommended in the IA32 Intel
of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since
the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of
debug tools should be aware of the potential incorrect debug event signaling created by
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO24.
IA32_MPERF Counter Stops Counting During On-Demand TM1
Problem:
According to the Intel
Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to
IA32_APERF (MSR E8H) should reflect actual performance while TM1 or on-demand
throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting while TM1
or on-demand throttling is activated, and the ratio of the two will indicate higher
processor performance than actual.
Implication:
The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state
(performance state) management algorithms under the conditions described above. It
is possible for the Operating System to observe higher processor utilization than actual,
which could lead the OS into raising the P-state. During TM1 activation, the OS P-state
request is irrelevant and while on-demand throttling is enabled, it is expected that the
OS will not be changing the P-state. This erratum should result in no practical
implication to software.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO25.
The Memory Controller tTHROT_OPREF Timings May be Violated
During Self Refresh Entry
Problem:
During self refresh entry, the memory controller may issue more refreshes than
permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING
CSR).
Implication:
The intention of tTHROT_OPREF is to limit current. Since current supply conditions near
self refresh entry are not critical, there is no measurable impact due to this erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
®
Architecture Software Developer's Manual, the use
®
64 and IA-32 Architectures Software Developer's Manual
27
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