Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 45
Specification update
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Status:
For the steppings affected, see the Summary Tables of Changes.
AAO86.
S1 Entry May Cause Cores to Exit C3 or C6 C-State
Problem:
Under specific circumstances, S1 entry may cause a logical processor to spuriously
wake up from C3 or C6 and transition to a C0/S1 state. Upon S1 exit, these logical
processors will be operating in C0.
Implication:
In systems where S1 is used for power savings, customers may observe higher S1
power than expected and software may observe a different C-state on S1 exit than on
S1 entry.
Workaround:
It possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO87.
Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
Problem:
When multiple performance counters are set to generate interrupts on an overflow and
more than one counter overflows at the same time, only one interrupt should be
generated. However, if one of the counters set to generate an interrupt on overflow is
the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated
when the IA32_FIXED_CTR2 overflows at the same time as any of the other
performance counters.
Implication:
Multiple counter overflow interrupts may be unexpectedly generated.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO88.
LBRs May Not be Initialized During Power-On Reset of the Processor
Problem:
If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last
Branch Records) may not be properly initialized.
Implication:
Due to this erratum, debug software may not be able to rely on the LBRs out of power-
on reset.
Workaround:
Ensure that the processor has completed its power-on reset cycle prior to initiating a
second reset.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO89.
Unexpected Interrupts May Occur on C6 Exit If Using APIC Timer to
Generate Interrupts
Problem:
If the APIC timer is being used to generate interrupts, unexpected interrupts not
related to the APIC timer may be signaled when a core exits the C6 power state. This
erratum may occur when the APIC timer is near expiration when entering the core C6
state.
Implication:
Due to this erratum, unexpected interrupt vectors could be sent from the APIC to a
logical processor.
Workaround:
Software should stop the APIC timer (by writing 0 to the Initial Count Register) before
allowing the core to enter the C6 state.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
45
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