Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 38
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AAO59.
System May Hang if
MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL Commands Are
Not Issued in Increasing Populated DDR3 Rank Order
Problem:
ZQCL commands are used during initialization to calibrate DDR3 termination. A ZQCL
command can be issued by writing 1 to the
MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL (Device 4,5,6, Function 0, Offset
15, bit[15]) field and it targets the DDR3 rank specified in the RANK field (bits[7:5]) of
the same register. If the ZQCL commands are not issued in increasing populated rank
order then ZQ calibration may not complete, causing the system to hang.
Implication:
Due to this erratum the system may hang if writes to the
MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL field are not in increasing
populated DDR3 rank order.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO60.
Package C3/C6 Transitions When Memory 2x Refresh is Enabled May
Result in a System Hang
Problem:
If ASR_PRESENT (MC_CHANNEL_{0,1}_REFRESH_THROTTLE_SUPPORT CSR function
0, offset 68H, bit [0], Auto Self Refresh Present) is clear which indicates that high
temperature operation is not supported on the DRAM, the memory controller will not
enter self-refresh if software has REF_2X_NOW (bit 4 of the MC_CLOSED_LOOP CSR,
function 3, offset 84H) set. This scenario may cause the system to hang during C3/C6
entry.
Implication:
Failure to enter self-refresh can delay C3/C6 power state transitions to the point that a
system hang may result with CATERR being asserted. REF_2X_NOW is used to double
the refresh rate when the DRAM is operating in extended temperature range. The
ASR_PRESENT was intended to allow low power self refresh with DRAM that does not
support automatic self refresh.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO61.
Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
Problem:
When back-to-back uncorrected machine check errors occur that would both be logged
in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16])
field may reflect the status of the most recent error and not the first error. The rest of
the IA32_MC3_STATUS MSR contains the information from the first error.
Implication:
Software should not rely on the value of IA32_MC3_STATUS.MSCOD if
IA32_MC3_STATUS.OVER (bit [62]) is set.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
38
Specification Update
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