Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 41
Specification update
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AAO70.
CPURESET Bit Does Not Get Cleared
Problem:
CPURESET (bit 10 of SYRE Device 8; Function 2; Offset 0CCH) allows the processor to
be independently reset without assertion of the PLTRST# signal upon a 0 to 1
transition. The CPURESET bit does not get cleared and must be cleared by software.
Implication:
The processor will not be reset if a 1 is written to this bit while it is already a one.
Workaround:
The CPURESET bit must be cleared by software prior to setting it.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO71.
PHOLD Disable in MISCCTRLSTS Register Does Not Work
Problem:
PHOLD Disable (PCI Hold Disable, bit [23] in MISCCTRLSTS Device 0; Function 0;
Offset 188H) does not function as described. Setting this bit will not cause the
processor to respond with Unsupported Request and log a fatal error upon receiving an
Assert_PHOLD message from the PCH (Platform Controller Hub).
Implication:
Due to this erratum, it is not possible to disable PHOLD requests from the PCH.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO72.
PCIe PMCSR Power State Field Incorrectly Allows Requesting of the
D1 and D2 Power States
Problem:
The PCIe PMCSR (Power Management Control and Status Register, Device 3,4,5,6;
Function 0; Offset E4H) incorrectly allows the writing/requesting of the D1 and D2
Power States in the Power State field (bits[1:0] of PMCSR) when these states are not
supported.
Implication:
Given that the device does not support the D1 and D2 states, attempts to write those
states should have been ignored. The PCIe port does not change power state from D0
or D3hot when the Power State bits are written to D1 or D2, so there is no functional
impact to the PCIe port. However, the Power State field is incorrectly modified.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO73.
PECI Accesses to Registers May Fail When Processor is Transitioning
to/from Package C6 Power State
Problem:
A PECI (Platform Environment Control Interface) access to PCI configuration registers
while the device is transitioning to or from package C6 may fail. Writes may not update
the target register and reads may return incorrect data. The PECI bus will not show any
indication the transaction failed.
Implication:
PECI accesses to PCI configuration registers may not be processed correctly.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
41
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