Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 26
Specification update
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AAO19.
Delivery Status of the LINT0 Register of the Local Vector Table May be
Lost
Problem:
The Delivery Status bit of the LINT0 Register of the Local Vector Table will not be
restored after a transition out of C6 under the following conditions
•
LINT0 is programmed as level-triggered
•
The delivery mode is set to either Fixed or ExtINT
•
There is a pending interrupt which is masked with the interrupt enable flag (IF)
Implication:
Due to this erratum, the Delivery Status bit of the LINT0 Register will unexpectedly not
be set. Intel has not observed this erratum with any commercially available software or
system.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO20.
Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
Problem:
The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts
instructions that load new values into segment registers. The value of the count may be
inaccurate.
Implication:
The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or
lower than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO21.
#GP on Segment Selector Descriptor that Straddles Canonical
Boundary May Not Provide Correct Exception Error Code
Problem:
During a #GP (General Protection Exception), the processor pushes an error code on to
the exception handler's stack. If the segment selector descriptor straddles the
canonical boundary, the error code pushed onto the stack may be incorrect.
Implication:
An incorrect error code may be pushed onto the stack. Intel has not observed this
erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAO22.
Improper Parity Error Signaled in the IQ Following Reset When a Code
Breakpoint is Set on a #GP Instruction
Problem:
While coming out of cold reset or exiting from C6, if the processor encounters an
instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is
enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly
logged resulting in an MCE (Machine Check Exception).
Implication:
When this erratum occurs, an MCE may be incorrectly signaled.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
26
Specification Update
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