Intel BV80605001914AG - Processor - 1 x Xeon X3430 Specification page 29

AAO30. OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific
lnternal Error
Problem: If a specific type of internal unclassified error is detected, as identified by
IA32_MCi_STATUS.MCACOD=0x0405, the IA32_MCi_ STATUS.OVER (overflow) bit [62]
may be erroneously set.
Implication: The OVER bit of the MCi_STATUS register may be incorrectly set for a specific internal
unclassified error.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAO31. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service
Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an
End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
AAO32. Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
Problem: Under a specific set of conditions, MMX stores (MOVD, MOVQ, MOVNTQ, MASKMOVQ)
which cause memory access faults (#GP, #SS, #PF, or #AC), may incorrectly update
the x87 FPU tag word register.
This erratum will occur when the following additional conditions are also met.
• The MMX store instruction must be the first MMX instruction to operate on x87 FPU
state (i.e. the x87 FP tag word is not already set to 0x0000).
• For MOVD, MOVQ, MOVNTQ stores, the instruction must use an addressing mode
that uses an index register (this condition does not apply to MASKMOVQ).
Implication: If the erratum conditions are met, the x87 FPU tag word register may be incorrectly set
to a 0x0000 value when it should not have been modified.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
Specification Update
29