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To test the single-clock, multiple-edge, state acquisition (logic analyzer)
Create a Compare file with the pattern 01010101 (if you are at this step as a return
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from step 10, the pattern will be 10101010). Use the following to create a Compare
file:
a a Press Run. The display should show alternating 0s and 1s. Verify the pattern by
scrolling through the display.
b b Press the List key. In the pop up menu, use the RPG knob to move the cursor to
Compare. Press Select.
c c In the Compare menu, move the cursor to Copy Listing to Reference, then press the
Select key.
d d Move the cursor to Specify Stop Measurement and press the Select key. Press Select
again to turn on Compare. At the pop up menu, select Compare. Move the cursor to
the Equal field and press the Select key. At the pop up menu, select Not Equal. Press
Done.
e e Move the cursor to the Reference Listing field and select. The field should toggle to
Difference Listing.
Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained
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without the "Stop Condition Satisfied" message appearing, then the test passes.
Press Stop to halt the acquisition. Record the Pass or Fail results in the performance
test record.
Test the next clock.
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a a Press the Format key, then select Master Clock.
b b Turn off and disconnect the clock just tested.
c c Repeat steps 4, 6 and 7 for the next clock listed in the table in step 4, until all clocks
have been tested.
Enable the pulse generator channel 1 COMP (with the LED on).
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