Agilent Technologies E8257D PSG User Manual page 254

Peripheral Devices
N5102A Digital Signal Interface Module
Figure 12-1
Least significant bit
See the PSG User's Guide for information
The N5102A module clock rate is set using the
400 MHz. The sample rate is automatically calculated and has a range of 1 kHz to 100 MHz. These
ranges can be smaller depending on logic type, data parameters, and clock configuration.
Maximum Clock Rates
The N5102A module maximum clock rate depends on the logic and signal type.
Table 12- 2 show the warranted rates and the maximum clock rates for the various logic and signal
types. Notice that LVDS in the output mode using an IF signal is the only logic type where the
warranted and maximum rates are the same.
Table 12-1 Warranted Parallel Output Level Clock Rates and Maximum Clock Rates
Warranted Level Clock Rates
Logic Type
IQ Signal Type
LVTTL and CMOS 100 MHz
LVDS 200 MHz
a.The IF signal type is not available for a serial port configuration.
240
Data Setup Menu for a Parallel Port Configuration
Most significant bit
IF Signal Type
100 MHz
400 MHz
softkey and has a range of 1 kHz to
Clock Rate
Maximum Clock Rates (typical)
a IQ Signal Type
150 MHz
400 MHz
Clock and sample rates
Table 12- 1
IF Signal Type
150 MHz
400 MHz
and
Chapter 12