Related Manuals for Intel IQ80333
Summary of Contents for Intel IQ80333
- Page 1 ® Intel IQ80333 I/O Processor Customer Reference Board Manual February 2005 Document Number: 306690001US Intel Part Number: C90183-001...
- Page 2 TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd. *Other names and brands may be claimed as the property of others.
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Page 3: Table Of Contents
Component References ... 10 Terms and Definitions ... 11 ® Intel 80333 I/O Processor ...12 ® Intel IQ80333 I/O Processor Evaluation Platform Board Features ... 14 Getting Started... 15 Kit Content ... 15 Hardware Installation ... 15 2.2.1 First-Time Installation and Test...15 2.2.2 Power Requirements ... - Page 4 Intel® IQ80333 I/O Processor Contents 3.7.1 Console Serial Port... 35 3.7.2 JTAG Debug ... 36 3.7.2.1 JTAG Port ... 36 Board Reset Scheme... 37 Switches and Jumpers... 38 3.9.1 Switch Summary... 38 3.9.2 Default Switch Settings of S7A1- Visual ... 38 3.9.3...
- Page 5 IQ80321 and IQ80333 Comparisons... 51 Getting Started and Debugger ... 53 Introduction ... 53 B.1.1 Purpose ... 53 B.1.2 Necessary Hardware and Software ...53 B.1.3 Related Documents ... 53 B.1.4 Related Web Sites ...54 Setup ...55 B.2.1 Hardware Setup ... 55 B.2.2...
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Page 6: Board Form Factor ..................................................................................................................... 26
80333 I/O Processor Functional Block Diagram... 25 Board Form Factor ... 26 ® Intel IQ80333 I/O Processor Evaluation Platform Board Peripheral Bus Topology... 31 Flash Connection on Peripheral Bus ... 32 JTAG Port Pin-out ... 36 10 RESET Sources ... 37 11 Default Switch Setting Switch S7A1 ... - Page 7 41 Peripheral Bus Memory Map ... 47 ® 42 Intel IQ80321 Evaluation Platform Board and ® Intel IQ80333 I/O Processor Evaluation Platform Board Comparisons ... 51 43 Related Documents ...53 Customer Reference Board Manual Intel® IQ80333 I/O Processor ® 80333 I/O Processor ...30...
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Page 8: Revision History
Intel® IQ80333 I/O Processor Contents Revision History Date March 2005 Revision Initial Intel® Developer Web Site Release (http://developer.intel.com/design/iio/). Customer Reference Board Manual February, 2005 Description... -
Page 9: Introduction
This document describes the Intel using DDR-II 400 MHz SDRAM. The Intel intelligent I/O development. The 80333 is a multi-function device that integrates the Intel XScale core (ARM* architecture compliant) with intelligent peripherals including a PCI Express bus application bridge. -
Page 10: Electronic Information
Intel® IQ80333 I/O Processor Introduction Electronic Information Table 2. Electronic Information Support Type The Intel World-Wide Web (WWW) Location: Customer Support (US and Canada): Component References Table 3 provides additional information on the major components of 80333. Table 3. Component Reference... -
Page 11: Terms And Definitions
In-Circuit Emulator – A piece of hardware used to mimic all the functions of a microprocessor. I/O processor Joint Test Action Group – A hardware port supplied on Intel XScale JTAG evaluation boards used for in-depth testing and debugging. PPCI-X Primary PCI-X. -
Page 12: Intel ® 80333 I/O Processor
PCI Express Specification, Revision 1.0. The Primary Address Translation Unit is compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a definitions of an ‘application bridge’. For more in depth information in regards to the 80333, please see the Intel Developer’s Manual. ®... -
Page 13: Intel ® 80333 I/O Processor Block Diagram
Intel® IQ80333 I/O Processor Introduction ® Figure 1. Intel 80333 I/O Processor Block Diagram Customer Reference Board Manual... -
Page 14: Intel ® Iq80333 I/O Processor Evaluation Platform Board Features
• 1 64-bit PCI-X connector - 133 MHz. • 1 64 bit 100 MHz PCI-X • Intel(R) 82545EM Gigabit Ethernet Controller also on the 100 MHz PCI. Dual RJ11 serial port connectors. The 80333 has two integrated UART serial ports which are 16550 compatible. -
Page 15: Getting Started
(read as ‘by eight’) edge connector. Note: Please note, at this time the IQ80333 does NOT work in a passive backplane. This is due to the nature of the PCI Express linking protocol. For the I/O processor to successfully come out of reset, a link must be established on the PCI Express bus. -
Page 16: Power Requirements
Intel® IQ80333 I/O Processor Getting Started 2.2.2 Power Requirements The 80333 requires a 3.3 V supply coming through the PCI Express primary connector. Plug the board into a desktop with a PCI Express slot. The 80333 has an auxiliary power receptacle (J1A1, see is used to power the secondary PCI-X slot. -
Page 17: Factory Settings
• TimeSys* Linux* RTOS • Accelerated Technology Inc.*, Nucleus Plus* RTOS and Development Tools Please contact your Intel representative for the latest updates or visit http://www.intel-ioprocessortools.com/kshowcase/view. 2.4.2 Contents of the Flash The production version of the board contains an image for RedHat RedBoot* target monitor. -
Page 18: Target Monitors
Intel® IQ80333 I/O Processor Getting Started Target Monitors 2.5.1 RedHat RedBoot RedBoot* is an acronym for “RedHat Embedded Debug and Bootstrap”, and is the standard embedded system debug/bootstrap environment from RedHat, replacing the previous generation of debug firmware: CygMon and GDB stubs. It provides a bootstrap environment for a range of embedded operating systems, such as embedded Linux and eCos*, and includes facilities such as network downloading and debugging. -
Page 19: Host Communications Examples
The host computer, when loaded with the proper software can communicate with the board. Figure 3. JTAG Debug Communication Laptop computer Customer Reference Board Manual Intel® IQ80333 I/O Processor Getting Started (Figure 2). Please note that the evlaution (Figure 3). Please note that the evaluation... -
Page 20: Network Communication
Intel® IQ80333 I/O Processor Getting Started 2.6.3 Network Communication Using a standard network connection, the user can communicate with the board via the ethernet port. Redboot also allows the user to remotely boot the platform using a BOOTP server through the network Connection. -
Page 21: Gnupro Gdb/Insight
Description: terminal emulator runs on host and communicates with the board via the serial cable. Start: Power up the IQ80333. While the 'reset' is asserted, the two 7-segment LEDs sequentially display “88”, “A0” through “A6”, followed by “SL” (Scrub loop). When RedBoot is successfully booted, it displays the characters “A1”... - Page 22 • Flow Control: none — Start HyperTerminal: • Select Call from HyperTerminal panel. — Reset or power up IQ80333. — The Host screen reads: RedBoot(tm) debug environment - built dd:mm:yy, Mon dd 2004 Platform: 80333 Copyright (C) 2004, RedHat, Inc.
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Page 23: Connecting With Gdb
(GDB) break main • Set breakpoint at main. (GDB) continue • Start the program using 'continue' verse the usual 'run'. • Program hits break at main() and wait. To be supplied separately. Customer Reference Board Manual Intel® IQ80333 I/O Processor Getting Started... - Page 24 Intel® IQ80333 I/O Processor Getting Started This Page Left Intentionally Blank Customer Reference Board Manual...
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Page 25: Hardware Reference Section
RS-232 GPIOs JTAG Customer Reference Board Manual DDR II 400 DDR SDRAM Battery Backup Intel® PCI-X Bus Slot (133 MHz) 80333 PCI-X Bus IOP (100 MHz) Processor X8 Edge Connector Intel® IQ80333 I/O Processor Hardware Reference Section Slot Slot Gig-E... -
Page 26: Board Form-Factor/Connectivity
The 80333 has two PCI-X expansion slot. The 80333 has two serial ports and one RJ-45 Ethernet port. The 80333 has one JTAG port compliant with ARM Multi-ICE 20-pin connector standard. The JTAG is targeted for the Intel ® XScale core and the CPLD, and is used for software debug purposes. -
Page 27: Power
Power The 80333 draws power from the PCI Express bus. The power requirements for the 80333 are shown Table 7 below. The numbers do not include the power required by a PCI-X card mounted on the expansion slot. Table 7. Power Features Voltage Rail +3.3 V... -
Page 28: Memory Subsystem
Unbuffered DIMMs, Registered DIMMs, and discrete DDR SDRAM devices. This IQ80333 has DDR-II at 400 MHz DIMM on the board. The memory subsystem of the evaluation board consists of the SDRAM as well as the Flash memory subsystems. -
Page 29: Flash Memory Requirements
Total Flash memory size is 8 MB. Table 8. Flash Memory Requirements IQ80333 Total Flash size is 8 MB 80333 Flash technology is based on Intel StrataFlash 80333 Flash uses a 16-bit interface 80333 Flash utilizes the 80333 Peripheral Bus 80333 May be programmed using the PCI-X interface –... -
Page 30: Interrupt Routing
Intel® IQ80333 I/O Processor Hardware Reference Section Interrupt Routing 80333 Interrupt routing. Table 9. External Interrupt Routing to Intel ® 80333 I/O Processor Interrupt HPI# S_INTA# S_INTB# S_INTC# S_INTD# P_INTA# P_INTB# P_INTC# P_INTD# System Resource Temperature Sensor, Header PCI-X Slot INTB#, Header... -
Page 31: Intel ® Iq80333 I/O Processor Evaluation Platform Board Peripheral Bus
Board Peripheral Bus The 80333 populates the peripheral bus as depicted by ® Figure 7. Intel IQ80333 I/O Processor Evaluation Platform Board Peripheral Bus Topology Intel® 80333 I/O Processor PBI Bus PC 104 Connector The devices on the bus include Flash ROM, audio buzzer, CPLD, HEX display, NVSRAM, and rotary switch. -
Page 32: Flash Rom
Intel® IQ80333 I/O Processor Hardware Reference Section 3.6.1 Flash ROM Table 11. Flash ROM Features Flash is an Intel StrataFlash Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 8. Flash Connection on Peripheral Bus... -
Page 33: Uart
3.6.3 Non-Volatile RAM In addition to the 8MB Flash device, the IQ80333 has a separate 32 K by 8 non-volatile RAM device on the peripheral bus. The NVRAMs address range is from CE87 0000 to CE87 FFFF (in hex). Please see Section 4.2.2, “Peripheral Bus Memory Map”... -
Page 34: Battery Status
Intel® IQ80333 I/O Processor Hardware Reference Section 3.6.7 Battery Status IQ80333 A CPLD on the Bus Memory Map” on page 47 Table 13. Battery Status Buffer Requirements Read/ Write Battery Present Battery Charged Battery Discharged Battery Enable Reserved provides the following status for the battery. -
Page 35: Debug Interface
3.7.1 Console Serial Port The platform has two serial ports for debug purposes as described in I/O Processor Evaluation Platform Board Peripheral Bus” on page Customer Reference Board Manual Intel® IQ80333 I/O Processor Hardware Reference Section Section 3.6, “Intel® IQ80333... -
Page 36: Jtag Debug
Intel® IQ80333 I/O Processor Hardware Reference Section 3.7.2 JTAG Debug The 80333 has a 20-pin JTAG connector (J7D2) that is in compliant with ARM Multi-ICE guidelines. 3.7.2.1 JTAG Port Figure 9. JTAG Port Pin-out VTref Vsupply nTRST RTCK nSRST DBGRQ... -
Page 37: Board Reset Scheme
RESETIN B_RST# PWRDELAY Intel® 80333 I/O Processor A_RST# TRST TRST CPLD SRST PWRGD Isolation Pwrgood PCI-E Con Intel® IQ80333 I/O Processor Hardware Reference Section list the reset schemes for the 80333. PCI-X Con B PCI-X Con A RST# LAN_PWR_GOOD 82545EM... -
Page 38: Switches And Jumpers
Intel® IQ80333 I/O Processor Hardware Reference Section Switches and Jumpers 3.9.1 Switch Summary Please note that the term ‘open’ refers to the individual pin of switch S7A1 being pushed in at bottom (small dot on pin away from the ‘open’ label on the switch). The term ‘closed’ refers to the pin being pushed in at the top. -
Page 39: Jumper Summary
J2D2 GPIO Header Definition Customer Reference Board Manual Description Description Signal Signal GPIO5 GPIO7 GPIO4 GPIO6 GPIO3 Intel® IQ80333 I/O Processor Hardware Reference Section Factory Default Open 1-2, 3-4 Open Open Section 2.2.2, “Power Requirements” shows the GPIO signal assignments. The Signal GPIO2... -
Page 40: Detail Descriptions Of Switches/Jumpers
S7A1-2: Reset I/O Processor Core Corresponding to Signal Name PBI_AD5 RESET MODE is latched at the de-asserting edge of P_RST# and it determines when the 80333 is held in reset until the Intel XScale ® 80333 I/O Processor Reset Description Section 3.6.6, “Rotary Switch”... -
Page 41: S7A1-3: Configration Cycle Enable Corresponding To Signal Name Pbi_Ad6
Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode S7A1-6 Open Hot Plug on Bus B Enabled Closed Disables Hot Plug on Bus B(Default mode) Customer Reference Board Manual Intel® IQ80333 I/O Processor Hardware Reference Section Operation Mode Operation Mode Operation Mode Operation Mode Operation Mode... -
Page 42: Switch S7A1 - 7: Smbus Manageability Address Bit 0
Intel® IQ80333 I/O Processor Hardware Reference Section 3.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 Corresponding to Signal Name PBI_AD17 This allows 80333 to address SMBus Slave Address bit 0 (PBI_A17). Table 27. Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode... -
Page 43: Jumper J7D1: Flash Bit-Width
3.9.6.5 Jumper J7D1: Flash bit-width The IQ80333 expects an 8-bit Flash enable. Table 31. Jumper J7D1: Descriptions Jumper J7D1 8-bit Flash Enable Table 32. Jumper J7D1: Settings and Operation Mode Pins Enables 16-bit Flash 8-bit Flash (default mode) 3.9.6.6 Jumper J1C1: JTAG Chain Table 33. -
Page 44: Jumper J7B4: Smbus Header
Intel® IQ80333 I/O Processor Hardware Reference Section 3.9.6.8 Jumper J7B4: SMBus Header Table 37. Jumper J7B4: Descriptions Jumper J7B4 SMBus Header Table 38. Jumper J7B4: Settings and Operation Mode J7B4 Pins 1, 2 Connects SM_SCLK to EEPROM U7B2 (Default Mode). -
Page 45: Software Reference
See the Intel 80333 I/O Processor Design Guide, section 8, table 34 for supported DDR333 and DDR-II configurations. For all registers relating to DRAM and other MCU related registers, see the Intel Processor Developer’s Manual. Components on the Peripheral Bus The 80333 has a peripheral bus which contains the following peripheral devices: •... -
Page 46: Flash Rom
0x0 on the 80333 Internal Bus. By default, address 0x0 is pointing to PCE0 where Flash is located. Currently, the Intel Flash Recovery Utility (FRU) can be used with the IQ80333. Another alternative to FRU would be to reprogram the Flash through JTAG or using Redboot commands, when Redboot is currently loaded onto the board. -
Page 47: Peripheral Bus Memory Map
64 KB 8-bit 64 KB 8-bit 64 KB 8-bit 64 KB 8-bit 64 KB 8-bit Intel® IQ80333 I/O Processor Software Reference Description Flash memory (re-mapped) Product Code Board Stepping CPLD Firmware Revision Discrete LEDs Hex Display Left Hex Display Right... -
Page 48: Board Support Package (Bsp) Examples
Intel® IQ80333 I/O Processor Software Reference Board Support Package (BSP) Examples Examples provided in this section are based on the RedHat* RedBoot software running on the IQ80333. ® 4.3.1 Intel 80333 I/O Processor Memory Map Figure 13 depicts the memory space for the 80333 (before RedBoot boots): ®... -
Page 49: Redboot* Intel ® 80333 I/O Processor Memory Map
0xF010 0000 0xFFF0 0000 4.3.3 RedBoot Intel Attached in the kit, find a copy of the RedHat eCos for IQ80333 CD. Once the CD is installed, you may find: • The RedBoot initialization code source files from the following location: From the installed directory: ..\RedHat\eCos\packages\hal\arm\xscale\iq80333\current\include... -
Page 50: Redboot Intel ® 80332 I/O Processor Ddr
Intel® IQ80333 I/O Processor Software Reference 4.3.4 RedBoot Intel Memory Initialization Sequence In order to set the correct ECC bits, a DDR memory system (DIMM or discrete components) must be written to with a known value. This process requires 64-bit writes to the entire DDR memory intended for use. -
Page 51: Iq80321 And Iq80333 Comparisons
Bus with chip-enable 0 (PCE0) Serial Debug Port Two UARTs integrated within the 80333. Network Debug Port Intel® 82545EM GbE on the 100 MHz PCI-X bus Intel® 82544 GbE on the PCI-X bus Rotary Switch Same LED HEX Display Same... - Page 52 Intel® IQ80333 I/O Processor IQ80321 and IQ80333 Comparisons This Page Left Intentionally Blank Customer Reference Board Manual...
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Page 53: Getting Started And Debugger
JTAG Support White Paper. B.1.1 Purpose The purpose of this appendix is to help the user setup and become familiar with the IQ80333 and other related hardware and software. This appendix steps the user through an example program using: •... -
Page 54: Related Web Sites
Intel® IQ80333 I/O Processor Getting Started and Debugger B.1.4 Related Web Sites • Macraigor: http://www.ocdemon.net/ • http://developer.intel.com/design/intelxscale/dev_tools/021022/index.htm • http://developer.intel.com/design/iio/ • http://developer.intel.com/design/iio/papers/273961.htm Customer Reference Board Manual... -
Page 55: Setup
Setup B.2.1 Hardware Setup Figure 14 and the rest of the Intel set up the hardware. • Connect the Raven to the host via the parallel port and to the evaluation board via the 20-pin JTAG connector. Note: The parallel port must be configured to EPP mode for the Macraigor Raven to work properly. -
Page 56: Software Setup
Intel® IQ80333 I/O Processor Getting Started and Debugger B.2.2 Software Setup MGC Code|Lab is a plug-in to Microsoft Visual Studio .NET, therefore Microsoft Visual Studio .NET must already be loaded on the system. To load MGC Code|Lab, run setup.exe under the program directory. -
Page 57: New Project Setup
“View, Solution Explorer”. 6. Right click on “Project80333” and select “Save Project80333”. 7. From http://developer.intel.com/design/iio/swsup/Tester1LED.htm, download the following zip file (…/Tester1LED) from the Software Support section, containing the example code files to the newly created project folder: Tester1LED.zip... -
Page 58: Configuration
Intel® IQ80333 I/O Processor Getting Started and Debugger B.3.2 Configuration Examine the main menu of Code|Lab EDE for .NET. • File • Edit Since Code|Lab is a plug-in to Visual Studio, some of these menu items are Visual Studio and some are specific to Code|Lab. -
Page 59: Flashing With Jtag
This Flash programmer only supports certain file formats: Intel Hex, Motorola srec and standard elf (executable and linking format). RedBoot.s19 and RedBoot.srec are both srec files. Macraigor offers conversion tools to convert existing file types to a supported file type. These... -
Page 60: Using Flash Programmer
Intel® IQ80333 I/O Processor Getting Started and Debugger B.4.2 Using Flash Programmer Note: The parallel port must be set to EPP mode or the Macraigor Raven does not work properly. Download the RedBoot executable files from the following location: http://developer.intel.com/design/intelxscale/dev_tools/021022/index.htm for the IQ80333. -
Page 61: Debugging Out Of Flash
Note: Rebuild cleans and builds. Clean deletes the old .o files in the project and build compiles, links, and produces the executable files. 3. When there are errors, carefully go back through Customer Reference Board Manual Intel® IQ80333 I/O Processor Getting Started and Debugger Section B.3.2, “Configuration”. -
Page 62: Running The Code|Lab Debugger
Intel® IQ80333 I/O Processor Getting Started and Debugger Running the Code|Lab Debugger This section is provided to get the system up and running in the Code|Lab Debug environment, but it is not intended as a full-functional tutorial. Please refer to the MGC Code|Lab Debug Reference Manual for more detailed information. -
Page 63: Displaying Source Code
5. Press “Go” again and notice that the program loop is infinite. 6. Press the “Halt” icon to stop execution. 7. Close the debugger and cycle power to the board. Customer Reference Board Manual Intel® IQ80333 I/O Processor Getting Started and Debugger... -
Page 64: Stepping Through The Code
Intel® IQ80333 I/O Processor Getting Started and Debugger B.7.5 Stepping Through the Code The “led.c” file contains a function that is called from code in “blink.c”. This exercise steps through the code and utilizes a few of the most common step tools. -
Page 65: Exploring The Code|Lab Debug Windows
Memory window. The ATU header begins at 0xffffe100 and contains a known number (8086). Also look at the base and limit registers for the memory and Flash devices, at 0xffffe508 and ffffe688 respectively, since they were initialized by RedBoot. Use the Intel Manual, to see what the values mean. -
Page 66: Registers Window
Intel® IQ80333 I/O Processor Getting Started and Debugger B.8.6 Registers Window Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this window. -
Page 67: Debugging Basics
B.9.2 Hardware and Software Breakpoints The following section provides a brief overview of breakpoints. See the Intel Developer’s Manual, for more detailed information. B.9.2.1 Software Breakpoints Software breakpoints are setup and utilized via debugger utilities (such as Code|Lab). -
Page 68: Exceptions/Trapping
Intel® IQ80333 I/O Processor Getting Started and Debugger B.9.3 Exceptions/Trapping A debug exception causes the processor to re-direct execution to a debug event handling routine. The ® Intel 80200 processor debug architecture defines the following debug exceptions: • instruction breakpoint •...