Layout Guidelines For Motherboards; Motherboard Example Configuration - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
Clocking Guidelines
6.2

Layout Guidelines for Motherboards

For motherboard implementations, the designer has much more flexibility with PCI clocking,
primarily related to controlling the central clock resources. Skew requirements for the motherboard
are more stringent due to the uncertainty of having PCI edge connectors on the secondary bus.
For motherboard implementation designs, it is best to choose a central clocking resource with enough
PCI clock outputs to drive all PCI devices in the system, including the
PCI devices on the secondary bus. All trace lengths should be equalized to both the primary and
secondary PCI devices. If it is not possible to find a central clock resource with enough clock outputs
for your design, then use a clock buffer/driver for the secondary PCI bus as shown in
To minimize skew for these designs, use the following equation for trace length (see
Equation 6-1. A = B + C + F = B + D + F - 2.5 Inches
The total trace length must be under 18 inches. Also, since implementations can be varied, each
design must be simulated to meet specifications as per PCI Local Bus Specification, Revision 2.1.
To minimize skew, clocks to connectors should be 2.5 inches shorter than traces routed to
motherboard devices.
Figure 6-16. Motherboard Example Configuration
Central
Clock
Resource
NOTES:
1. Trace length between source component and resistor must be <1 inch.
2. All resistor values are 22 Ohms.
3. To minimize skew, trace length A = B + C = B + D - 2.5 inches.
4. F is the length of the feedback path in the clock generator.
28
A
See notes 1,2,3,4
B
PLL
PCLKO
Clock
Generator
PCLK1
PCLK3
FB
PCLK2
*
D
C
D
RM/RN I/O processor and any
Figure 6-16.
Figure 6-16):
Primary PCI Connector
PCI DEVICE
2.5"
80960RM/RN
P_CLK
Secondary PCI Connector
PCI DEVICE
2.5"
Secondary
PCI Device
Design Guide