Intel Iq80960Rm/Rn Sdram Battery Backup Pld Equations - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
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Intel IQ80960RM/RN SDRAM Battery Backup PLD Equations
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Intel IQ80960RM/RN SDRAM Battery
Backup PLD Equations
MODULE BATT
//TITLE
//PATTERN101-1809-01
//REVISION
//AUTHORJ. Neumann
//COMPANYCyclone Microsystems Inc.
//DATE
//CHIP
// 1/20/98 Modify target device to PALLV16V8Z-20JI
//Initial release.
PRSTn
SCKE0
SCKE1
OUT0
OUT1
EQUATIONS
// If SDRAM clock enable goes low, SDRAM clock enable
// must be held low to ensure that the SDRAM is held in auto refresh mode.
// Reset going high will release the hold on SCKE.
OUT0 = SCKE0.PIN & PRSTn//SCKE is the set term, PRSTn is the reset term
SCKE0 = 0;
SCKE0.OE = !OUT0;//When OUT = 0, SCKE is grounded
OUT1 = SCKE1.PIN & PRSTn
SCKE1 = 0;
SCKE1.OE = !OUT1;
92
SDRAM Battery Backup Enable
10/30/97
PALLV16V8Z-20JI
PIN 9;//Primary PCI reset
PIN 13; //SDRAM bank 0 clock enable
PIN 16; //SDRAM bank 1 clock enable
PIN 14; //SCKE0 output enable
PIN 17; //SCKE1 output enable
# SCKE0.PIN & OUT0.PIN
# !SCKE0.PIN & PRSTn;
# SCKE1.PIN & OUT1.PIN
# !SCKE1.PIN & PRSTn;
*
//When OUT = 1, SCKE is high impedance
E
Design Guide