Pullups And Pulldown Resistors - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor 5 V and 3.3 V Design Considerations
9.5 V
CCPLL
To reduce clock skew on the processor, the V
isolated on the pinout. The low-pass filter, shown in
and its effects on timing relationships in system designs. The trace lengths between the 4.7 µF
capacitor, the 0.01 µF capacitor, and V
There are three V
pin requires a low-pass filter. Providing just one low-pass filter and tying it to all three V
inputs is not recommended.
Figure 9-21. V Low-Pass Filter
CCPLL
V
(Board Plane)
9.6

Pullups and Pulldown Resistors

RM/RN I/O processor
appropriate supply voltage. In a 3.3V only design, the resistor should be tied to the 3.3V supply. In
a design where the
be tied to either the 3.3V power island or the 5V supply.
38
Pins Requirement
pins on the
C C PL L
10Ω, 5%, 1/8W
CC
inputs which require a pull-up should have the pullup resistor tied to the
RM/RN I/O processor
pin for the Phase Lock Loop (PLL) circuit is
C C P L L
Figure 9-21, reduces noise induced clock jitter
must be as short as possible.
CCPLL
RM/RN I/O processor: V
CCPLL
+
4.7µF
0.01µF
*
interface to components operating at 5V, the resistors can
, V and V . Each
1 2 3
CCPLL CCPLL
C C PL L
V
CCPLL
(Processor input pin)
Design Guide