Sdram Guidelines; Sdram Interface Signals - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
4.2

SDRAM Guidelines

The RM/RN I/O processor
SDRAM. The memory controller supports 16 Mbit or 64 Mbit technology offering up to 128
Mbytes of ECC protected memory. For low-cost solutions, the memory controller provides a 32-bit
SDRAM interface offering up to 64 Mbytes of memory.
Table 4-3
Table 4-3.

SDRAM Interface Signals

Pin Name
DCLKOUT
DCLKIN
SCKE[1:0]
SDQM[7:0]
SCE[1:0]#
SWE#
SBA[1:0]
SA[10]
SA[11:0]
SRAS#
SCAS#
DQ[63:0]
SCB[7:0]
14
memory controller supports up to two banks of 66 MHz, 72-bit
shows the SDRAM interface signals.
SDRAM Clock Out - This is the clock to the off-chip SDRAM clock buffer driven by the
RM/RN I/O processor.
SDRAM Clock In - This is the clock returning from the off-chip SDRAM clock buffer.
Section 4.2.2 describes the SDRAM clocking strategy.
Clock enables - One clock after SCKE[1:0] is deasserted, the data is latched on DQ[63:0]
and SCB[7:0]. The burst counters within the SDRAM device are not incremented.
Deasserting this signal places the SDRAM in self-refresh mode. For normal operation,
SCKE[1:0] must be asserted.
Data Mask - On a write, these signals disable the data on a byte-by-byte basis, thus
preventing certain bytes from being written. On a read, two clocks after asserting
SDQM[7:0] the output data bytes from the SDRAM device are disabled.
Chip Select - Must be asserted for all transactions to the SDRAM device. One per bank.
Write Enable - Controls the SDRAM data input buffers. Asserting SWE# causes the data on
DQ[63:0] and SCB[7:0] to be written into the SDRAM devices.
SDRAM Bank Selects - Controls which of the internal SDRAM banks to read or write. For
16 Mbit devices (2 banks), only SBA[0] is used while 64 Mbit devices use SBA[1:0].
Address bit 10 - If high during a read or write command, then auto-precharge occurs after
the command. During a row-activate command, this bit is part of the address.
Address bits 11 through 0 - Indicates the row or column to access depending on the state of
SRAS# and SCAS#.
Row Address Strobe - Indicates that the current address on SA[11:0] is the row.
Column Address Strobe - Indicates that the current address on SA[11:0] is the column.
Data Bus - 64-bit wide data bus.
ECC Bus - 8-bit error correction code which accompanies the data on DQ[63:0].
Description
Section 4.2.2 describes the SDRAM clocking strategy.
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Design Guide