External Power Failure Logic In The System - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
Figure 4-13. External Power Failure Logic in the System
Controller
The implementation illustrated in
The edge detect state machine activates the pull-down when the MCU deasserts SCKE[1:0]. As
long as V
of P_RST# deactivates the pull-down. The memory controller will reliably control SCKE[1:0] at
this point, driving it low. The pull-down is activated within the PLD device. Refer to the
IQ80960RM/RN schematics in
Note: Figure 4-13
that two signals are required (one per SDRAM bank) and the above logic should be replicated for
each SCKE[1:0].
24
Memory
SCKE
out
P_RST#
Figure 4-13
is active, SCKE[1:0] is held low. Once the memory controller is reset, the rising edge
batt
Appendix E
shows logic for one of the SCKE signals. The loading of this signal is large enough so
Address, Data, and Control
SCKE[0]
External PLD
PULLCKE
requires that all external logic be powered by V
for details.
*
SDRAM
Subsystem
.
batt
Design Guide