Layout Guidelines; Dual-Bank Sdram Memory Subsystem - Intel i960 Design Manual

4.2.1

Layout Guidelines

The SDRAM subsystem may be implemented with:
•
up to two banks directly connected on the printed circuit board (32, 64, or 72 bits wide)
•
up to two 168-pin DIMM sockets (64-bit data bus with or without ECC)
•
up to two 144-pin SO-DIMM sockets (64-bit data bus without ECC)
The memory controller supports either one dual-bank DIMM or two single-bank DIMMs. The
4-Clock 66 MHz 72-bit ECC Unbuffered SDRAM DIMM Specification requires four clock inputs.
Figure 4-4
processor
clock routing, refer to
Figure 4-4.

Dual-Bank SDRAM Memory Subsystem

Design Guide
illustrates how two banks of 16 Mbits SDRAM would interface with the
memory controller. SBA[1] is only connected for 64 Mbit SDRAM devices. For the
Figure 4-10.
80960RM/RN
DQ[63:0]
SCB[7:0]
SRAS#
SCAS#
SWE#
SA[10:0]
SBA[0]
SBA[1]
SDQM[7:0]
SCKE
SCE0#
SCE1#
Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
*
RM/RN I/O
DQ[63:0]
CB[7:0]
RAS#
CAS# SDRAM DIMM
using 16 Mbit
WE#
devices
A[10:0]
BA0
DQM[7:0]
CKE[1:0]
CS[3:0]#
DQ[63:0]
CB[7:0]
RAS#
SDRAM DIMM
CAS#
using 16 Mbit
WE#
devices
A[10:0]
BA0
DQM[7:0]
CKE[1:0]
CS[3:0]#
15