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10.5
Control and Operation of SDRAM Interface
10.5.1
Initializing SDRAM
To use the SDRAM, it must be initialized by following the procedure below.
1. Initializing the SDRAMC registers
Set up the SDRAMC registers in the following order:
(1) SDRAMC_CFG register
Set the SDRAM size, address configuration and access timing parameters.
(2) SDRAMC_REF register
Set the auto-refresh and self-refresh counters.
(3) SDRAMC_INIT register
Set SDON to 1 to enable SDRAMC.
(4) SDRAMC_APP register
Set the CAS latency. Also enable double frequency mode if necessary.
2. Waiting after SDRAM power-on
After the power to the SDRAM is turned on, a NOP state (#SDCS = 1) must be maintained at least for a certain
length of time (e.g., 100 µs or 200 µs). Because this duration varies with each SDRAM, refer to the specifica-
tions of the SDRAM being used.
3. Executing an SDRAM initial sequence
In order to initialize the SDRAM, the PALL (Precharge All banks), REF (Auto Refresh), and MRS (Mode
Register Set) commands must be executed sequentially. Note that the initialization sequence depends on the
SDRAM used.
Example 1: PALL → REF → REF → MRS (→ EMRS)
Example 2: PALL → MRS → REF → REF (→ REF → REF → REF → REF → REF → REF)
Refer to the specifications of the SDRAM to be used for the initialization sequence.
Each command can be executed separately using the control bit shown below.
To execute the PALL (Precharge All) command:
Write 0x12 to the SDRAMC_INIT register to set INIPRE to 1.
Then write any data to any address in the SDRAM. This dummy write causes the PALL command to be
sent to the SDRAM.
To execute the REF (Auto Refresh) command:
Write 0x11 to the SDRAMC_INIT register to set INIREF to 1.
Then write any data to any address in the SDRAM. This dummy write causes the REF command to be sent
to the SDRAM.
When executing the REF command twice or more, insert the nop instruction between the executions.
REF command execution → nop instruction execution → REF command execution (→ REF → nop →
REF...)
The SDRAM timing parameters set in the SDRAMC_CFG register is disabled when this initialization se-
quence is executed. Therefore, enough number of nop instructions must be executed to satisfy the SDRAM
timings.
To execute the MRS/EMRS (Mode Register Set/Extended Mode Register Set) command:
Write 0x14 to the SDRAMC_INIT register to set INIMRS to 1.
Then write any data to a specific address of SDRAM shown below according to the CAS latency (MRS) or
extended mode parameters (EMRS).
S1C33L26 TECHNICAL MANUAL
Seiko Epson Corporation
10 SDRAM CONTROLLER (SDRAMC)
10-7
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