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1.12.0 SYSTEM PARITY CHECKING
AND PARITY GENERATION
Various errors that occur in the system are
recorded in the processing unit error byte and in
the port error byte. These errors can be dis-
played on the CE control panel and are described
in 7.2.1. Parity checking and parity generation
throughout the system are described here.
Odd parity (by byte) is maintained in the proc-
essing unit data flow. To ensure correct parity,
parity checking stations and parity generating
stations are provided throughout the processing
unit. These checking and parity generating sta-
tions are illustrated in the diagram on this page.
151.------,----i
Control
Storage
(2
bytes)
Main
Storage
(1 byte)
I
SAR
CK 1
Parity predict circuits check the ALU portion of
the processing unit. By analyzing the operation
being performed and the input data, parity pre-
dict circuits predict whether the output of ALU
requires a parity bit or not. Parity predict cir-
cuits generate the parity bit if it is required.
The parity at the output of ALU is compared to
the output of the parity predict circuits to de-
termine whether the ALU is working correctly.
Processing Unit
Adr
Adr
Sw
Camp
====:Dl~:~,pp------t/
OR
Display
High
Byte
t::l1~~=32~L7SR=S~~
15
OR
PC
=
Parity Check
PG
=
Parity Generate
PP
=
Parity Predict
1-12
Sys Bus Out Low
Channel SBI
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