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1.11.0 MICRO INTERRUPTS
The processing unit performs computations in a
step-by-step procedure; one micro instruction is
executed followed by the next sequential micro
instruction. This sequence of micro instructions
can be changed by a branch instruction; or the
main program level might be interrupted by a
micro interrupt.
The system has four levels of micro interrupts:
level 0, level 1, level 2, and level 3. Level 0 has the
highest priority and level
3
the lowest. Interrupts
having a higher priority take precedence over those
having a lower priority. For example, a micro
interrupt on level
0
interrupts the processing of a
micro interrupt on level 1.
The micro interrupt levels are assigned as follows:
Level
o
1
2
3
Description
Machine check
Disk drive
Keyboard, BSCA/SDLC, and printer
MCU, magnetic character reader,
or data recorder attachments
The display screen and 33FD cannot cause micro
interrupts
A machine check interrupt (level
0)
occurs when-
ever the system detects a processing unit parity
check, invalid address, or microprogram check. A
machine check interrupt can also be initiated by
a port check. The preceding checks are described
in 7.2.0.
A level 1 micro interrupt occurs whenever the disk
drive requires attention.
The BSCA/SDLC, keyboard, and printer operate on
micro interrupt level 2. Further priorities are set
within level 2; the priorities are:
1.
BSCA/SDLC
2.
Keyboard
3.
Printer
Micro interrupt level 3 can be used by the mag
card unit, magnetic character reader, or data
recorder attachment features.
Micro interrupt level 0 shares a set of work reg-
isters with the main program level microroutines.
Levels 1, 2, and 3 each have a unique set of work
registers in the LSR stack.
Micro interrupt level 3 uses the first 10 LSRs of
the reserved 32 LSR group for its work and MARl
MAB registers.
I nterrupt levels 4 and 5 are reserved. Registers 2A
through 3F of the additional 32 LSR group are
reserved to support interrupt levels
4
and
5.
The set of LSRs for each micro interrupt level
consists of:
8
16-bit work registers
MAR (microprogram address register) to
store the address of the next micro in-
struction to be executed.
MAB (microprogram address backup) to
store the return address when a branch and
link instruction is executed
- - - -
- - - - - -
- - -
LSR
Stack
Used by the
base system
Mall)
Level
Level
Level
Level
0
1
2
-
~
'rV1icro Interrupt
0
(Machine Check)
"--
Also used by
rrviai n Program Level
rr:::1,cro Interrupt
1
""- (Disk)
r-
Micro Interrupt
2
(Keyboard, Printer,
~d
BSCA/SDLC)
Used by optional
features
Micro Interrupt
3
(Optional Features)
Level 3
_r
L
r-
L
I
L-
r
L
Hex
Register
Address
Work Registers
WRD
I
00
WRl
i
01
WR2
i
02
WR3
!
03
WR4
i
04
WR5
j
05
WR6
1
06
WR7
07
Address Registers
MAR (Ml)
08
MAB (Ml)
09
MAR (0)
OA
MAB
(0)
OB
MAR (1)
OC
MAB (1)
OD
MAR (2)
OE
MAB (2)
OF
Work Registers
WRO
WR1
WR2
WR3
WR4
WR5
WR6
WR7
Work Registers
WRO
WRl
WR2
WR3
WR4
WR5
WR6
WR7
Work Registers
WRD
WRl
WR2
WR3
WR4
WR5
WR6
WR7
10
11
12
13
14
15
16
17
18
19
lA
1 B
lC
lD
1 E
1 F
20
21
22
23
24
25
26
27
Address Registers
Introduction
1-11
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