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0
0
PROC RUNl
DE~F0123DE~F 123DE~F 123DE~F
12
3
~.6:\I~~Y~TOR
ALTER MAR
C
4C
4C
4C
4
·IRPT
B
5
B
5
B
5
B
5
• DPL Y STOR
A
6
A
6
A
6
A
6
.6~SL~SJ~~~
9
8
7
9
R
7 2
9
8
7 3
9
8
7 4
• INSN STEPI
I
I
·
DPLY PCR
~--DISPLAY/DATA----l
l
L - - - - - - - - A D D R E S S / D A T A - - - - - - - - - - - - - '
MODE
SEL~~~~~SN
STEP
DPLY PWR CHK
RESET
o
PWR
FORCE
COMM
DPLY
ON
rlECK FAULT DPLY CLOCK
IPL
IMPL
fl
PREV
ON
DISKETTE
DISKETTE
CTL
0 0 0 0
OFF
DISK
DISK
MAIN
PROCINTERRUPT
000
4
2
1
o
1
2
3
0000
8
4
2
1
7.2.13 PWR FAULT DPLY Switch and
DPLY PWR CHK Key
When a system power failure occurs, the power
supply at fault and the type of failure ale stored
in latches. These latches are on the power
sequence card and retain their information as
long as the mainline switch is kept on. These
latches are called the present power fault
latches. When the RESET key is pressed and
power turned on, the information recorded in
the present power fault latches is transferred to
another set of latches called the previous power
fault latches. Thus, it is possible to store the
reason for a current power failure and the reason
for a preceding power failure in latches. The
contents of the power fault latches can be dis-
played even though power is down on the oper-
ator control panel.
To display the present power fault latches,
switch PWR FAULT DPL Y to the PRES posi-
tion, then press DPL Y PWR CHK key. If the
PWR FAULT DPL Y switch is in the PREV
position, the previous power fault latches are
displayed.
CEOT
The power fault conditions are displayed in the
high-order byte on the CE control panel. The
meaning of the specific bits is as follows:
Bits 0 and 1
01
Undervoltage
10
Overvoltage
11
Overcurrent
Bits 2 and 3
01
Multilevel filter assembly
11
Dual level filter assembly
Bits 4 through 7
0001
-4V at fault
0010
+5V at fault
0011
-5V at fault
0100
+6V at fault
Multilevel filter
0101
+8.5V at fault
assembly
0110
+12V at fault
0111
-12V at fault
1000
+24V at fault
}
Dual level filter
1001
-24V at fault
assembly
1111
Both level failing in the dual level filter
assembly or +5V, +8.5V, and -12V failing
in the multilevel filter assembly.
7-8
7.2.14 ADD COMP Switch
RUN Position
The ADD COMP switch in the RUN position is
used with the STO R SE L switch and the data
switches. An address compare synchronization
signal (A-A 1 J2D 12) is provided whenever the
address switches match an address in SAR. The
STOR SEL switch determines if main storage or
control storage is used for the compare.
STOP Position
The ADD COMP switch in the STOP position
is used with the STOR SEL switch and the data
switches. The system stops and an address com-
pare synchronization signal is provided whenever
the data switches match an address in SAR. The
STOR SEL switch determines if main storage
or control storage is used for the compare. The
time when the system stops is determined by
the following considerations:
1.
If the address compare is on a main stor-
age address, the emulator completes the
current system level instruction being
executed and then enters a stop micro-
program loop. The STOP light turns on.
The microprogram remains in this loop
until the START key is pressed.
2.
With the exception of I/O operations, an
address compare on a control storage
address stops the processing unit clock
after executing the micro instruction at
that address. To restart, the CE START
key must be pressed.
If an address compare stop is made on a
control storage address during the execu-
tion of a system instruction, the results of
that instruction are unpredictable.
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