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10.4.3 Interface Signal Timings
The timings described below are approximations
that will help to determine whether the timing
circuits are working. These timing circuits are
located on the FET card (G2), the AEO digital
card (E2)' and SNBU timing card (K3).
The signals shown here are generated by turning
the test/operate switch to T1 from an adjacent
reset position. Sync (minus) the oscilloscope on
'request to send' at 04G09.
Receiver Unclamp Time
I
- - - - -
Signal
Threshold
:
G2G03
:/
I
I
. .
1
I
I
1
G2D07
_ _ ---:-1 _ _ _ _ _ _ _ _ --,1/
I
I
~14~--------A----------~
1
..
+Clamp, -Resync
1
I
I-
B
"I
A -
Determined by CSCD strapping options.
(See strapping charts 10.4.5 through
10.4.11.)
B -
Extra delay of about 800 ms appears in
machines with auto equalizer at G2D07
('+clamp, -resync) before the signal settles
at the '-resync' level.
Clear-to-Send Time
~/
G2S10
---~
Request to Send
1
1
_ _ _ _ _ _ _ _
~/
G2S05
:
1- 0 11
.1----
AO.----.J ..
I
Clear to Send
!
I
I
I
1
T2D02
I
I
"'!
10-20
....-i4--B-~1
1
•
~r
to Send
(I
nterface)
I
I
1
1
1--1-.--------------
C
---------------1 .....
1
I
1
1
A -
Determined by CSCD strapping options.
(See strapping charts in this section.)
B -
Extra delay with long initial clear to send,
980 ms (AEO) or 1500 ms (SNBU). This
delay is 30 ms for SNBU without long
initial clear to send.
C - Clear to send delay as seen by DTE.
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