System Architecture; X3850 X6 - IBM x3850 X6 Planning And Implementation Manual

For more information about the additional power supplies, see 3.22, "Power subsystem" on
page 101.

2.2 System architecture

This section shows the overall architecture of both the x3850 X6 and x3950 X6.

2.2.1 x3850 X6

Figure 2-12 shows the system architecture of the x3850 X6 server.
MB 1
SMI
links
MB 2
Intel
Xeon
CPU 4
MB 1
MB 2
QPI links
MB 1
MB 2
Intel
Xeon
CPU 1
MB 1
MB 2
X6 DDR3
Compute Book
DMI
links
Figure 2-12 x3850 X6 system architecture
Processor-to-processor communication is carried over shared-clock or coherent quick path
interconnect (QPI) links. Each processor has three QPI links to connect to other processors.
PCIe 3.0 lanes
MB 1
MB 2
Intel
Xeon
CPU 3
MB 1
MB 2
MB 1
MB 2
Intel
Xeon
CPU 2
MB 1
MB 2
PCIe 3.0 lanes
PCIe
switch
Slot 1: PCIe 3.0 x16 (x16)
Slot 2: PCIe 3.0 x8 (x8)
Slot 3: PCIe 3.0 x8 (x8)
Half Length I/O Book
Slot 4: PCIe 3.0 x16 (x16)
Slot 5: PCIe 2.0 x8 (x8)
Slot 6: PCIe 3.0 x16 (x16)
Full Length I/O Book
Slot 7: PCIe 3.0 x16 (x16)
Slot 8: PCIe 3.0 x16 (x8)
Slot 9: PCIe 3.0 x16 (x16)
Slot 10: Mezz LOM (x8)
Primary I/O Book
Slot 11: PCIe 3.0 x16 (x8)
Slot 12: PCIe 3.0 x16 (x8)
Storage Book
8x USB
Intel
I/O Hub Serial
PCIe x1
IMM2 Management
Video
Chapter 2. Technology
19