IBM x3850 X6 Planning And Implementation Manual page 38

Slot 33: PCIe 3.0 x16 (x16)
Slot 34: PCIe 3.0 x8 (x8)
Slot 35: PCIe 3.0 x8 (x8)
Half Length I/O Book
Slot 36: PCIe 3.0 x16 (x16)
Slot 37: PCIe 2.0 x8 (x8)
Slot 38: PCIe 3.0 x16 (x16)
Full Length I/O Book
Slot 39: PCIe 3.0 x16 (x16)
Slot 40: PCIe 3.0 x16 (x8)
Slot 41: PCIe 3.0 x16 (x16)
Slot 42: Mezz LOM (x8)
Primary I/O Book
Slot 43: PCIe 3.0 x16 (x8)
Slot 44: PCIe 3.0 x16 (x8)
Storage Book
8x USB
Serial
PCIe x1
Management IMM2
Video
Figure 2-15 x3950 X6 system architecture (top half)
The 8-socket configuration is formed using the native QPI scalability of the Intel Xeon
processor E7 family.
Figure 2-16 shows how the processors are connected together using QPI links.
7
6
Figure 2-16 QPI connectivity - x3950 X6 with 8 processors installed
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IBM System x3850 X6 and x3950 X6 Planning and Implementation Guide
PCIe 3.0 lanes
MB 1
MB 2
MB 1
MB 2
MB 1
MB 2
MB 1
MB 2
PCIe 3.0 lanes
Intel PCIe
I/O Hub switch
DMI links
8 4
5 1
x3950 X6 - 8 sockets
SMI
links
Intel Intel
Xeon Xeon
CPU 7 CPU 8
QPI links
Intel Intel
Xeon Xeon
CPU 6 CPU 5
QPI link (to CPU 1)
QPI link (to CPU 2)
3
2
QPI link (to CPU 3)
QPI link (to CPU 4)
MB 1
MB 2
MB 1
MB 2
MB 1
MB 2
MB 1
MB 2
X6 DDR3
Compute Book