IBM x3850 X6 Planning And Implementation Manual page 43

Each processor has some amount of memory, connected directly to the processor. To access
memory connected to another processor, each processor uses QPI links through another
processors. This design creates a non-uniform memory access (NUMA) system. Similarly, I/O
can be local to a processor or remote through another processor.
For QPI use, Intel modified the MESI cache coherence protocol to include a forwarding state.
Therefore, when a processor asks to copy a shared cache line, only one other processor
responds.
For more information about QPI, visit the following web page:
http://www.intel.com/technology/quickpath
Intel Data Direct I/O
For I/O, Intel no longer has a separate I/O hub. It now integrates PCI Express 3.0 I/O into the
processor itself. Data Direct I/O helps to optimize data transfer between local CPU and PCIe
devices. The combination of Data Direct I/O and PCI 3.0 provides a significantly higher I/O
performance with lower latencies and reduced power consumption.
For more information about Data Direct I/O, visit the following web page:
http://www.intel.com/content/www/us/en/io/direct-data-i-o.html
RAS features
The Intel Xeon processor E7 family of processors has additional reliability, availability, and
serviceability (RAS) features on their interconnect links (SMI and QPI):
Cyclic redundancy checking (CRC) on the QPI links:
The data on the QPI link is checked for errors.
QPI packet retry:
If a data packet on the QPI link has errors or cannot be read, the receiving processor can
request that the sending processor try resending the packet.
QPI clock failover:
If there is a clock failure on a coherent QPI link, the processor on the other end of the link
can become the clock. This action is not required on the QPI links from processors to I/O
hubs, as these links are asynchronous.
QPI self-healing:
If there are persistent errors detected on a QPI link, the link width can be reduced
dynamically to allow the system to run in a degraded mode until repair can be performed.
QPI link can reduce its width to a half width or a quarter width, and slowdown its speed.
Scalable memory interconnect (SMI) packet retry:
If a memory packet has errors or cannot be read, the processor can request that the
packet be resent from the memory buffer.
27
Chapter 2. Technology