IBM x3850 X6 Planning And Implementation Manual page 166

The options in the memory settings panel are as follows:
Memory Mode (Default: Independent):
This option enables Independent or Lockstep Memory Mode. In independent mode, all
channels operate independently with SMI links operating at twice the DDR3 speed. In
Lockstep mode, two channels operate synchronously, allowing advanced memory
protection. SMI link operations occur at the DDR3 speed.
Mirroring (Default: Disabled):
This option enables or disables memory mirroring as described in "Memory mirroring" on
page 33.
Memory mirror mode: Memory mirror mode cannot be used in conjunction with
Memory spare mode.
Sparing (Default: Disabled):
This option enables or disables memory rank sparing as described in "Rank sparing" on
page 34.
Memory Speed (Default: Max Performance):
This option sets the operating frequency of the installed DIMMs:
– Minimal Power provides less performance for better power savings. The memory
operates at the lowest supported frequency, which, in the X6 system, is 1333 MHz.
– Power Efficiency provides the best performance per watt ratio. The memory operates
one step under the rated frequency.
– Max Performance provides the best system performance. The memory operates at the
rated frequency, that is, 1600 MHz for DIMMs rated at 1600 MHz or higher.
Memory Power Management (Default: Disabled):
This option enables or disables Memory Power Management
Socket Interleave (Default: NUMA):
This option sets Socket Interleave to NUMA (Non Unified Memory Architecture) or
Non-NUMA. In NUMA mode, memory is not interleaved across processors. Non-NUMA,
memory is interleaved across processors.
Patrol Scrub (Default: Enable):
This option enables scheduled background memory scrubbing before any error is
reported, as opposed to default demand scrubbing on an error event. This option provides
better memory subsystem resiliency at the expense of a small performance loss.
Memory Data Scrambling (Default: Enable):
This option enables a memory data scrambling feature to further minimize bit-data errors.
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IBM System x3850 X6 and x3950 X6 Planning and Implementation Guide