X3950 X6 - IBM x3850 X6 Planning And Implementation Manual

If you want to take advantage of this recovery, it is important to carefully plan your network
and storage connectivity, because if CPU 1 fails, PCIe slots 9, 10, and 12 become
unavailable.

2.2.2 x3950 X6

The x3950 X6 server has the same architecture adapted to 8-socket configuration.
Figure 2-14 and Figure 2-15 show the system architecture of the x3950 X6 server
(Figure 2-15 shows the upper half, and Figure 2-14 shows the lower half).
QPI link (to CPU 7)
QPI link (to CPU 8)
MB 1
SMI
links
MB 2
Intel
Xeon
CPU 4
MB 1
MB 2
QPI links
MB 1
MB 2
Intel
Xeon
CPU 1
MB 1
MB 2
X6 DDR3
Compute Book
QPI link (to CPU 5)
QPI link (to CPU 6)
Figure 2-14 x3950 X6 (bottom half)
PCIe 3.0 lanes
MB 1
MB 2
Intel
Xeon
CPU 3
MB 1
MB 2
MB 1
MB 2
Intel
Xeon
CPU 2
MB 1
MB 2
PCIe 3.0 lanes
PCIe
switch
DMI links
Slot 1: PCIe 3.0 x16 (x16)
Slot 2: PCIe 3.0 x8 (x8)
Slot 3: PCIe 3.0 x8 (x8)
Half Length I/O Book
Slot 4: PCIe 3.0 x16 (x16)
Slot 5: PCIe 2.0 x8 (x8)
Slot 6: PCIe 3.0 x16 (x16)
Full Length I/O Book
Slot 7: PCIe 3.0 x16 (x16)
Slot 8: PCIe 3.0 x16 (x8)
Slot 9: PCIe 3.0 x16 (x16)
Slot 10: Mezz LOM (x8)
Primary I/O Book
Slot 11: PCIe 3.0 x16 (x8)
Slot 12: PCIe 3.0 x16 (x8)
Storage Book
8x USB
Intel
I/O Hub Serial
PCIe x1
IMM2 Management
Video
Chapter 2. Technology
21