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Bit 4
This bit is the complement of the clear to send (-CTS) input. Setting bit 4 (loop) of
the MCR to a logicall, is equivalent to RTS in the MCR.
Bit 5
This bit is the complement of the data set ready (-DSR) input.
If
bit 4 (loop) of the
MCR is set to a logicall, this bit is equivalent to DTR in the MCR.
Bit 6
This bit is the complement of the ring indicator (-RI) input.
If
bit 4 (loop) of the MCR
is set to a logical l, this bit is equivalent to -OUT 1 in the MCR.
Bit 7
This bit is the complement of the received line signal detect (-RLSD) input.
If
bit 4
(loop) of the MCR is set to a logicall, this bit is equivalent to -OUT 2 of the MCR.
Receiver Buffer Register
The receiver buffer register contains the received character as defined below:
Receive Buffer Register
Read Only DLAB
=
0
(Hex Address n230, n238, n240)
Bit
7
6
5
4
3
2
1
a
EDatabitO
Data bit 1
Data bit 2
.
Data bit 3
-
. .
Data bit 4
-
. .
Data bit 5
-
~
Data bit 6
-
. .
Data bit 7
-
Bit 0 is the least significant bit and is the first bit serially received.
28
5080 Peripheral Adapter
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