Description - IBM RT Series Hardware Reference Manual

Description
The
mM
5080 Peripheral Adapter provides three serial output ports on a 4.25- by 13. 12-inch board
that plugs into one I/O position. The adapter system control signals and voltage requirements are
provided
throu~
a 2- by 31-position and a 2- by 18-position tab on the bottom of the adapter.
Up to four adapters may be used in one RT PC system. A DIP switch on the adapter is used to
assign the adapter I/O address range. The port I/O address assignments are contained in the
adapter's I/O address range.
The adapter is fully programmable and supports asynchronous communications only. It adds and
removes start bits, stop bits, and parity bits. A programmable baud-rate generator allows operation
from 50 bps to 19200 bps. Five-, 6-, 7- or 8-bit characters with 1, 1-1/2, or 2 stop bits are
supported. A priority interrupt system controls transmit, receive, error, line status, and data set
interrupts.
Three 10-pin male connectors on the adapter provide external access to the three ports.
The heart of the adapter is an NS 16450 LSI chip or a functional equivalent. Features in addition to
those listed above include:
Note: The NS 16450 is functionally equivalent to all INS8250.
• Full double buffering that eliminates the need for precise synchronization
• Independent receiver clock input
• False start bit detection
• Line-break generation and detection.
All communications protocol is a function of the system microcode that must be loaded before the
adapter is operational. All pacing of the interface and control signal status must be handled by the
system software. Figure 1 on page 2 is a block diagram of the IBM 5080 Peripheral Adapter.
5080 Peripheral Adapter 1