IBM RT Series Hardware Reference Manual page 69

Register Select (AO, AI, A2),
Pins
26-28: These three inputs are used during a read or write
operation to select an NS16450 register to read from or write into as indicated in Figure 11. Note
that the state of the divisor latch access bit (DLAB), which is the most significant bit of the line
control register, affects the selection of certain NS16450 registers. The DLAB must be set high by
the system software to access the baud-generator divisor latches.
DLAB A2 At AO Register
0 0 0 0 Receiver Buffer (Read)
Transmitter Holding Register (Write)
0 0 0 1 Interrupt Enable
x 0 1 0 Interrupt Identification (Read Only)
x 0 1 1 Line Control
x 1 0 0 Modem Control
x 1 0 1 Line Status
x 1 1
0
Modem Status
x 1 1 1 Scratch
1 0 0 0 Divisor Latch (Least Significant Byte)
1
0 0
1 Divisor Latch (Most Significant Byte)
Figure 11. NS16450 Register Selection
Master Reset (MR), Pin 35: When high, this signal clears all the registers (except the receive buffer,
transmitter holding, and divisor latches), and the control logic of the NS16450. Also, the state of
various output signals (SOUT, INTRPT, -OUT 1, -OUT 2, -RTS, -DTR) is affected by an active
MR input. Refer to the table in Figure 12 on page 14 for reset functions.
5080 Peripheral Adapter 13