IBM RT Series Hardware Reference Manual page 80

Interrupt Enable Register
This 8-bit register enables the four types of interrupts of the NS 16450 to separately activate the
chip interrupt (INTRPT) output signal. The interrupt system can be totally disabled by resetting
bits 0 through 3 of the interrupt enable register. Similarly, by setting the appropriate bits of this
register to a logical 1, selected interrupts can be enabled. Disabling the interrupt system inhibits the
interrupt identification register and the active (high) INTRPT output from the chip. All other
system functions operate in their normal manner, including the setting of the line status and modem
status registers. The contents of the interrupt enable register are described below:
Bit 0
Bit 1
Bit 2
Bit 3
Bits 4-7
Interrupt Enable Register DLAB
=
0
(Hex Address n231, n239, n241 )
Bit 7 6 5 4
3
2 1 0
I I
I :
Enable data available interrupt
Enable Tx holding register
empty interrupt
Enable receive line status
interrupt
-
Enable modem status
..
interrupt
-
=
0
--
- .
=
0
..
-.
=
0
--
-
=
0
--
This bit enables the received data available interrupt when set to logical 1.
This bit enables the transmitter holding register empty interrupt when set to logical 1.
This bit enables the receiver line status interrupt when set to logical 1.
This bit enables the modem status interrupt when set to logical 1.
These four bits are always logical O.
24 5080 Peripheral Adapter