IBM RT Series Hardware Reference Manual page 443

Interrupt Identification Register (Hex XFA):
The controller
has an on-chip interrupt capability that makes communications
possible with all of the currently popular microprocessors. In
order to minimize programming overhead during data character
transfers, the controller prioritizes interrupts into four levels:
receiver line status (priority 1), received data ready (priority 2),
transmitter holding register empty (priority 3), and modem status
(priority 4).
Information about a pending prioritized interrupt is stored in the
interrupt identification register (IIR). (See the figure "Interrupt
Control Functions," later.) The IIR, when addressed during
chip-select time, stops the pending interrupt with the highest
priority, and no other interrupts are acknowledged until the
processor services that particular interrupt.
Interrupt Identlflcltlon Register
Ihex
XFA)
Bit 7 6 5 4 3 2 1 0
~>
0
"""rr"~
',"di".
>
Interrupt ID Bit 0
>
Interrupt ID Bit 1
>
=0
>
=0
>
=0
>
=0
>
=0
Interrupt Identification Register
Bit 0
Bits 1-2
Bits 3-7
This bit can be used in either hard-wired, prioritized,
or polled conditions to indicate if an interrupt is
pending. When bit 0 is logical 0, an interrupt is
pending, and the IIR contents may be used as a
pointer to the appropriate interrupt service routine.
When bit 0 is logical 1, no interrupt is pending, and
polling (if used) continues.
These two bits identify the pending interrupt that has
the highest priority interrupt pending, as shown in
the following figure.
These five bits are always logical O.
Serial/Parallel Adapter 9