IBM RT Series Hardware Reference Manual page 100

Bits 8-9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Memory Mode
Bit
98
00 = System write operation
01
=
Overlay write operation
10
=
Adapter write operation
11
=
Automatic read/write operation
Address Counter Mode
o
=
Increase the address counter
1
=
Decrease the address counter
Address Counter Stepping
o =
Y stepping
1
=
X stepping
Bits 10 and 11 control whether the LSB of a bit map memory operation is accessed
from the left, right, above or below the MSB. See "Bit Map Memory Operations"
on page
S.
for further explanation.
Block transfer
Bit 12 controls block transfer mode. When this bit is set from a 0 to a 1, the
address of the next memory location accessed is stored in a pointer register on
the card. This address is adjusted to point at the next memory location at the
end of each memory cycle. That is, the X or Y address is increased or
decreased. After the first block transfer memory cycle has loaded the on-card
pointer register, the memory address supplied on the data bus is ignored, and
the pointer is used to access memory. To reload the pointer register, either
clear and set the block transfer bit again or read from the block transfer reload
I/O address, X'01S2'.
Interrupt enable
If bit 13 is 1, an interrupt is generated at the start of vertical sync. If this bit is
0, the interrupt is not generated. See "Interrupts" on page 11.
Sync enable (always 1)
Video enable
o
=
Disables video to monitor
1
=
Enables video to monitor
8 Advanced Color Graphics Display Adapter