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Automatic Read/Write Operation (Mode
=
11)
In this mode of operation, data is alternately read into D 1, D2 and D3 and then written to memory
with successive write operations from the microprocessor. Data read from memory is not gated
onto any busses external to the data path, but is used only to update Dl, D2 and D3. This allows
the relatively fast 'Store' operation to be used for block transfer operations with no 'Loads'
required.
To get the alternate read/write operations into phase with the source and destination addresses, the
system processor should do a 'Load' operation from the first source address. Subsequent 'Stores'
will automatically alternate between read and writes to the bit map.
110 Operations
In order to manipulate the various registers on the adapter, a set of I/O operations are required.
Data Mask Register (X'0162')
Typically these two 8-bit registers (DMI and DM2) are initialized with data representing the
inverse of each other, and are used to mask the bits on or off for logical combination through the
logic unit.
An 8 bit for DMI Mask (Data Bus MS Byte, bits 0-7)
An 8 bit for DM2 Mask (Data Bus LS Byte, bits 0-7).
Data Control Register (X'0160') Write Only
Bits 0 through 11 should not be changed for at least 1.4 microseconds after a memory operation
since the memory operation may still be in progress.
Bits 0-2
Rotate Count
The rotate count determines the number of bits that the data read from the bit
map is shifted to the left prior to being written back into the bit map. This
value has no effect during system write or overlay write modes.
It
has effect
only during adapter write or automatic write modes.
6
Advanced Monochrome Graphics Display Adapter
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