IBM RT Series Hardware Reference Manual page 450

Modem Status Register (Hex XFE):
The 8-bit MSR provides
the current state of the control lines from the modem (or external
device) to the processor. In addition, four bits of the MSR
provide change information. These four bits are set to logical 1
whenever a control input from the modem changes state. They
are reset to logical 0 whenever the processor reads this register.
MI~lm
Stltus RIglstlr Ihlx XFEI
Bit
7 6 5 4 3 2 1 0
~>
Delta
mea<"
Se'"
>
Delta Data Set Ready
>
Trailing Edge Ring Indicator
>
Delta Data Carrier Detect
>
Clear to Send
>
Data Set Ready
>
Ring Indicator
>
Data Carrier Detect
Modem Status Register
Bit 0 This bit is the delta c1ear-to-send (DCTS) indicator.
It indicates the
I
-CTS
I
input to the chip has
changed state since the last time it was read by the
processor.
Bit 1 This bit is the delta data-set-ready (DDSR)
indicator. It indicates the '-DSR
I
input to the chip
has changed state since the last time it was read by
the processor.
Bit 2 This bit is the trailing-edge ring-indicator (TERI)
detector. It indicates the
I -
RI
I
input to the chip has
changed from an active condition to an inactive
condition.
Bit 3 This bit is the delta data-carrier-detect (DDCD)
indicator. It indicates the '-DCD
I
input to the chip
has changed state.
Note: Whenever bit 0, 1, 2, or 3 is set to a logical
1, a modem status interrupt is generated.
16 Serial/Parallel Adapter