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before writing can take place. The processor output port address
for this register is 3CF.
Mode Register Format
Bit
7
6
5
4
3
2
1
0
I I
I I :
Write Mode
Test Condition
Read Mode
'-------~
Odd/Even
'--------~
Shift Register Mode
'---..&....--------~
Not Used
Bit O-Bit 1
Write Mode
Bit 2
Bits
1 0
o
0
Each memory plane is written with the
processor data rotated by the number of
counts in the rotate register, unless
Set/Reset is enabled for the plane. Planes
for which Set/Reset is enabled are written
with 8 bits of the value contained in the
Set/Reset register for that plane.
o
1
Each memory plane is written with the
contents of the processor latches. These
latches are loaded by a processor read
operation.
1 0
Memory plane n (0 through 3) is filled
with 8 bits of the value of data bit n.
1 1
Not Valid
The logic function specified by the function select
register also applies.
Test Condition-A logical 1 directs graphics
controller outputs to be placed in high impedance
state for testing.
IBM Enhanced Graphics Adapter 51
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