IBM RT Series Hardware Reference Manual page 182

Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Select Row Scan Counter-A logical 0 selects
row scan counter bit 1 on MA 14 output pin. A
logical 1 selects MA 14 counter bit on MA 14
output pin.
Horizontal Retrace Select-This bit selects
Horizontal Retrace or Horizontal Retrace divided
by 2 as the clock that controls the vertical timing
counter. This bit can be used to effectively
double the vertical resolution capability of the
CRT Controller. The vertical counter has a
maximum resolution of 512 scan lines due to the
9-bit wide Vertical Total Register. If the vertical
counter is clocked with the horizontal retrace
divided by 2 clock, then the vertical resolution is
doubled to 1024 horizontal scan lines. A logical
o
selects HR TC and a logical 1 selects HR TC
divided by 2.
Count By Two- When this bit is set to 0, the
memory address counter is clocked with the
character clock input. A logical 1 clocks the
memory address counter with the character clock
input divided by 2. This bit is used to create
either a byte or word refresh address for the
display buffer.
Output Control-A logical 0 enables the module
output drivers. A logical 1 forces all outputs into
high impedance state.
Address Wrap-This bit selects Memory Address
counter bit MA 13 or bit MA 15, and it appears
on the MA 0 output pin in the word address
mode. If you are not in the word address mode,
MA 0 counter output appears on the MA 0
output pin. A logical 1 selects MA 15. In
odd/ even mode, bit MA 13 should be selected
when the 64K memory is installed on the board.
Bit MA 15 should be selected when greater then
64 K memory is installed. This function is used to
implement Color Graphics Monitor Adapter
compatibility.
42 IBM Enhanced Graphics Adapter