IBM RT Series Hardware Reference Manual page 77

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Note: Bits 1 through 4 are the error conditions that produce a receiver line status
interrupt whenever any of the corresponding conditions are detected.
Bit S
This bit is the transmitter holding register empty (THRE) indicator. Bit 5 indicates
that the NS 16450 is ready to accept a new character for transmission. In addition, this
bit causes the NS16450 to issue an interrupt to the processor when the THRE interrupt
enable is set high. The THRE bit is set to a logical 1 when a character is transferred
from the transmitter holding register into the transmitter shift register. The bit is reset
to logical 0 concurrently with the loading of the transmitter holding register by the
processor.
Bit 6
This bit is the transmitter empty (TEMT) indicator. Bit 6 is set to a logical 1 whenever
the transmitter holding register (THR) and the transmitter shift register (TSR) are both
empty.
It
is reset to
a
logical 0 whenever either the THR or TSR contain a data
character. Bit 6 is a read-only bit.
Bit 7
This bit is permanently set to logical O.
Interrupt Identification Register
The NS16450 has an on-chip interrupt capability that allows for complete flexibility in interfacing to
microprocessors. To provide minimum software overhead during data character transfers, the
NS 16450 ranks interrupts into four levels:
Receiver line status (priority 1)
Received data ready (priority 2)
Transmitter holding register empty (priority 3)
Modem status (priority 4).
Information indicating that a priority interrupt is pending and information on the type of interrupt is
stored in the interrupt identification register. Refer to the "Interrupt Control Functions" table in
Figure 13 on page 23. The interrupt identification register (IIR), when addressed during
chip-select time, freezes the highest priority interrupt pending, and no other interrupts are
acknowledged until that particular interrupt is serviced by the processor. The contents of the IIR
are described below.
5080 Peripheral Adapter
21

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