IBM RT Series Hardware Reference Manual page 339

TNL SN20-9844 (March 1987) to 75X0235
Control/Status Register
I/O DATA FIELD
7
18
I I I I I
T -- -- ---
~
Bit 00 FRAME SYNC INT ENABLE (Read/Write)
Bit 01 GRAPHIC OP INTERRUPT ENABLE (Read/Write)
Bit 02 FRAME SYNC INTERRUPT STATUS (Ready Only)
Bit 03 GRAPHIC OP INTERRUPT STATUS (Read Only)
Bit 04 VIDEO ENABLE (Read)
Bit 05 BLACK ON WHITE BACKGROUND (Read/Write)
Bit 06 HORIZONTAL SYNC (Read Only)
Bit 07-15 RESERVED
Figure 19. Control/Status Register (Address X'ODI2')
Note: This register is initialized to
X'OOXX'
with a POR or reset adapter command.
This control/status register may be read or written by the system processor. The control/status
register contains the bits which enables processing, interrupts, and video. All bits in this register
are normally initialized at power on to the ofT or 0 state.
Frame Sync Int Enable (bit 0)
This bit, when active, places any frame sync interrupt on the channel interface
interrupt level 11. When inactive, no frame sync interrupts are placed on the
channel and the frame sync interrupt latch is reset.
Graphic Operation Interrupt Enable, (bit
1)
This bit, when active, places any graphic operations interrupt on the channel
interface interrupt level 11. When inactive, graphic operations interrupts are
not placed on the channel and the graphic operations interrupt latch is reset.
Status (bits 2 and 3)
The frame sync interrupt status and the graphic operations interrupt status bits
are read-only bits and indicate if these interrupts are active.
Extended Monochrome Graphics Adapter 27