IBM RT Series Hardware Reference Manual page 75

Bits 0, 1
Bit 2
Bit 3
Bit 4
BitS
Bit 6
Bit 7
These two bits specify the number of bits in each transmitted or received serial
character. The encoding of bits 0 and 1 is as follows:
Bit 1 Bit 0
Word Length
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
This bit specifies the number of stop bits in each transmitted or received serial
character. If bit 2 is a logical 0, one stop bit is generated or checked in the transmit or
receive data, respectively. If bit 2 is a logical 1 when a 5-bit word length is selected
through bits 0 and 1, 1-1/2 stop bits are generated or checked. If bit 2 is a logical 1
when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated or
checked.
This bit is the parity enable bit. When bit 3 is a logical 1, a parity bit is generated
(transmit data) or checked (receive data) between the last data word bit and stop bit of
the serial data. (The parity bit is used to produce an even or odd number of 1 's when
the data word bits and the parity bit are summed.)
This bit is the even parity select bit. When bit 3 is a logical 1 and bit 4 is a logical 0, an
odd number of logical 1 is transmitted or checked in the data word bits and parity bit.
When bit 3 is a logical 1 and bit 4 is a logical 1, an even number of bits are transmitted
or checked.
This bit is the stick parity bit. When bit 3 is a logical 1 and bit 5 is a logical 1, the
parity bit is transmitted and then detected by the receiver as a logical 0 (space parity) if
bit 4 is a logical 1, or as a logical 1 (mark parity) if bit 4 is a logical O.
This bit is the set break control bit. When bit 6 is a logical 1, the serial output (SOUT)
is forced to the spacing (logical 0) state and remains there regardless of other
transmitter activity. The set break is disabled by setting bit 6 to a logical O. This
feature enables the processor to alert a terminal in a computer communications system.
This bit is the divisor latch access bit (DLAB). It must be set high (logicall) to access
the divisor latches of the baud-rate generator during a read/write operation.
It
must be
set low (logical 0) to access the receiver buffer, the transmitter holding register, or the
interrupt enable register.
5080 Peripheral Adapter 19