Troubleshooting Rx2660 Cpu; Ipf Processor Load Order; Processor Module Behaviors; Customer Messaging Policy - HP Integrity rx2660 User's & Service Manual

Troubleshooting rx2660 CPU

The rx2660 server supports both single- and dual-core processors. Each rx2660 server supports
one or two IPF processor modules. The dual-core processor modules contain two individual
CPU cores. This results in four physical CPUs when two processor modules are installed in
rx2660 servers.
Furthermore, unlike previous IPF processor modules, each physical CPU core contains logic to
support two physical threads. This results in up to eight physical threads, or the equivalent of
eight logical CPUs, when two dual-core processor modules are installed and enabled in rx2660
servers (the operating system kernel attaches one or more software processes to each available
thread, so in multiple processor servers, having more threads means all software processes are
launched and executed faster).

IPF Processor Load Order

For a minimally loaded server, one IPF processor module must be installed in CPU slot 0 on the
system board, and its threads must be enabled by user actions. Additional processor modules
of the same revision are installed in CPU slot 1 for rx2660 servers.

Processor Module Behaviors

All enabled CPUs and their threads almost immediately become functional after system power
is applied. Each thread is in a race to fetch their instructions from their CPU instruction and data
caches to complete early self test and rendezvous.
Early code fetches come from PDH, until memory is configured. Then normal execution is fetched
from main memory.
Local MCA events cause the physical CPU core and one or both of its logical CPUs within that
IPF processor module to fail while all other physical and their logical CPUs continue operating.
Double-bit data cache errors in any physical CPU core causes a Global MCA event that causes
all logical and physical CPUs in the server to fail and reboot the operating system.

Customer Messaging Policy

• A diagnostic LED only lights for physical CPU core errors, when isolation is to a specific
IPF processor module. If there is any uncertainty about a specific CPU, then the customer
is pointed to the SEL for any action, and the suspect IPF processor module CRU LED on the
System Insight Display is not lighted.
• For configuration style errors, for example, when there is no IPF processor module installed
in CPU slot 0, all of the CRU LEDs on the diagnostic LED panel are lighted for all of the IPF
processor modules that are missing.
• No diagnostic messages are reported for single-bit errors that are corrected in both instruction
and data caches, during corrected machine check (CMC) events to any physical CPU core.
Diagnostic messages are reported for CMC events when thresholds are exceeded for single-bit
errors; fatal processor errors cause global / local MCA events.
Table 5-15 Processor Events That Light System Insight Display LEDs
Diagnostic Sample IPMI Events
LED(s)
Processors Type E0h, 39d:04d
BOOT_DECONFIG_CPU
Processors Type E0h, 5823d:26d
PFM_CACHE_ERR_PROC
126 Troubleshooting
Cause Source
Processor SFW
failed and
deconfigured
Too many WIN Agent
cache errors
detected by
processor
Notes
This event
follows other
failed
processor(s)
Threshold
exceeded for
cache parity
errors on
processor