Memory Configuration Submenu - Congatec COM Express conga-TC87 User Manual

Feature
DMI IOT
10.5.2.2

Memory Configuration Submenu

Feature
Memory Frequency
Total Memory
Memory Voltage
DIMM#0 (Bottom)
DIMM#2 (Top)
CAS Latency (tCL)
CAS to RAS (tRCDmin) no option
Row Precharge
(tRPmin)
Active to Precharge
(tRASmin)
Memory Frequency
Limiter
DDR Reset Wait Time
Max TOLUD
Enh Interleave Support
RI Support
DLL Weak Lock Support Disabled
Mc Lock
Ch Hash Support
Ch Hash Mask
Ch Hash Interleaved Bit BIT06, BIT07, BIT08,
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Options Description
Enabled Enable or disable DMI IOT.
Disabled
Options Description
no option Displays the memory frequency.
no option Displays the total amount of installed memory.
no option Displays the memory voltage.
no option Displays bottom memory socket DIMM information.
no option Displays top memory socket DIMM information.
no option Displays the CAS Latency (tCL).
Displays the CAS to RAS (tRCDmin).
no option Displays the Row Precharge (tRPmin).
no option Displays the Active to Precharge (tRASmin).
Auto, 1067,1333, 1600, Maximum memory frequency selections in [MHz].
1867, 2133, 2400, 2667
0-3000000 The amount of time to wait (in nano seconds) for switch DDR voltage.
Default : 0
Dynamic, 1 GB, 1.25 GB,
Maximum value of TOLUD Dynamic assignment would adjust TOLUD automatically based on largest
1.5 GB, MMIO length of installed graphic controller.
1.75 GB, 2 GB, 2.25 GB,
2.5 GB, 2.75 GB, 3 GB,
3.25 GB
Disabled Enable or disable Enhanced Interleave support.
Enabled
Disabled Enable or disable Rank Interleave support. Note: RI and HORI can not be enabled at the same time.
Enabled
Enable or disable DLL weak lock support.
Enabled
Disabled Enable or disable capacity to lock or not MC registers.
Enabled
Disabled Enable or disable channel hash support. Note: Only if memory interleaved mode.
Enabled
1-0x3FFF Set the bit(s) to be included in the XOR function. Note: Bit mask corresponds to bits[19:6].
Default : 0x30CE
Select the bit to be used for channel interleaved mode. Note: BIT07 will interleave the channels at a 2
BIT09 cacheline granularity, BIT08 at 4 and BIT09 at 8.
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