Nic Configuration Submenu; Chipset Setup; Platform Controller Hub (Pch) Submenu - Congatec COM Express conga-TC87 User Manual

10.4.19

NIC Configuration Submenu

Feature
Link Speed
Wake On LAN
10.5

Chipset Setup

Select the Chipset tab from the setup menu to enter the Chipset BIOS Setup screen. The menu is used for setting chipset features.
Main Advanced
Platform Controller Hub (PCH)
Processor (Integrated Components)
10.5.1

Platform Controller Hub (PCH) Submenu

Feature
Intel PCH SKU Name
PCI Express Clock Gating
DMI Link ASPM PCH Side
DMI Link Extended Synch
Control
Disconnect external SMBus
PCIe-USB Glitch W/A
USB Precondition
xHCI Idle L1
BTCG
Copyright © 2013 congatec AG
Options Description
Auto Negotiated Specifies the port speed used for the selected boot protocol.
10 Mbps Half
10 Mbps Full
100 Mbps Half
100 Mbps Full
Disabled Enables the server to be powered on using an in-band magic packet.
Enabled
Chipset
Options Description
no option Displays the SKU Name of the PCH.
Disabled Enable or disable PCI Express clock gating for each root port.
Enabled
Disabled Active State Power Management (ASPM) of DMI link PCH side. DMI link is the main bus between the
Enabled Processor and Platform Controller Hub (PCH).
Disabled The control of extended synch on PCH side of the DMI link.
Enabled
Never Allows to cut off the off-board SMBus segment. This can be a workaround for non spec conform external
During POST SMBus devices.
Always
Disabled PCIe-USB glitch W/A for bad USB device(s) connected behind PCIe/PEG port.
Enabled
Disabled Precondition work on USB host controller and root ports for faster enumeration.
Enabled
Enabled Enable or disable xHCI Idle L1. xHCI Idle L1 can be set to disable for PCH Ax stepping (early prototype) to
Disabled workaround USB3.0 hot plug will fail after 1 hot plug removal.
Enabled
Enable or disable USB related trunk clock gating.
Disabled
Boot Security Save & Exit
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